/* Register Map for the Si5351 Devices	*/
/*                                    	*/
/* Thomas Kuschel created 2022-05-10  	*/
/* KW4NZ Version 1.0                   	*/

#define SI5351_DEVICE_STATUS		0u	/* R */
#define SI5351_SYS_INIT		(1u<<7)	/* System Initialization Status, 0..System initialization is complete. Device is ready 1..Device is in system initalization mode. */
#define SI5351_LOL_B		(1u<<6) /* PLL B Loss Of Lock Status, 0..PLL B is locked, 1..PLL B is unlocked. */
#define SI5351_LOL_A		(1u<<5)	/* PLL A Loss Of Lock Status */
#define SI5351_LOS_CLKIN	(1u<<4)	/* CLKIN Loss Of Lock Status (Si5351 only) 0..Valid clock signal at the CLKIN pin */
#define SI5351_LOS_XTAL		(1u<<3)	/* Crystal Loss Of Signal. 0..Valid crystal signal at the XA and XB Pins */
#define SI5351_REVID_1		(1u<<1)
#define SI5351_REVID_0		(1u<<0)
#define SI5351_REVID		(3u<<0) /* Revision number of the device. */
#define SI5351_DEVICE_STATUS_RESET_VALUE	0x00

#define SI5351_INTERRUPT_STATUS_STICKY	1u	/* R/W */
#define SI5351_SYS_INIT_STKY	(1u<<7) /* System Calibration Status Sticky Bit. 0..No SYS_INIT interrupt has occured since it was last cleared. */
#define SI5351_LOL_B_STKY		(1u<<6) /* PLLB Loss of Lock Status Sticky Bit. 0..No PLL_B interrupt has occured since it was last cleared. */
#define SI5351_LOL_A_STKY		(1u<<5)
#define SI5351_LOS_CLKIN_STKY	(1u<<4)
#define SI5351_LOS_XTAL_STKY	(1u<<3)
#define SI5351_INTERRUPT_STATUS_STICKY_RESET_VALUE	0x00

#define SI5351_INTERRUPT_STATUS_MASK	2u
#define SI5351_SYS_INIT_MASK	(1u<<7)
#define SI5351_LOL_B_MASK		(1u<<6)
#define SI5351_LOL_A_MASK		(1u<<5)
#define SI5351_LOS_CLKIN_MASK	(1u<<4)
#define SI5351_LOS_XTAL_MASK	(1u<<3)
#define SI5351_INTERRUPT_STATUS_MASK_RESET_VALUE	0x00

#define SI5351_OUTPUT_ENABLE_CONTROL	3u	/* R/W */
#define SI5351_CLK7_OEB	(1u<<7) /* Output Disable for CLKx. 0..Enable CLKx output. 1..Disable CLKx output. */
#define SI5351_CLK6_OEB	(1u<<6)
#define SI5351_CLK5_OEB	(1u<<5)
#define SI5351_CLK4_OEB	(1u<<4)
#define SI5351_CLK3_OEB	(1u<<3)
#define SI5351_CLK2_OEB	(1u<<2)
#define SI5351_CLK1_OEB	(1u<<1)
#define SI5351_CLK0_OEB	(1u<<0)
#define SI5351_OUTPUT_ENABLE_CONTROL_RESET_VALUE	0x00

#define SI5351_OEB_PIN_ENABLE_CONTROL_MASK	9u	/* R/W */
#define SI5351_OEB_MASK7	(1u<<7)	/* OEB pin enable control of CLKx. 0..OEB pin controls enable/disable state of CLKx output */
#define SI5351_OEB_MASK6	(1u<<6) /*  1..OEB pin does not control enable/disable state of CLKx output. */
#define SI5351_OEB_MASK5	(1u<<5)
#define SI5351_OEB_MASK4	(1u<<4)
#define SI5351_OEB_MASK3	(1u<<3)
#define SI5351_OEB_MASK2	(1u<<2)
#define SI5351_OEB_MASK1	(1u<<1)
#define SI5351_OEB_MASK0	(1u<<0)
#define SI5351_OEB_PIN_ENABLE_CONTROL_MASK_RESET_VALUE	0x00

#define SI5351_PLL_INPUT_SOURCE		15u	/* R/W */
#define SI5351_CLKIN_DIV_1	(1u<<7)
#define SI5351_CLKIN_DIV_0	(1u<<6)
#define SI5351_CLKIN_DIV	(3u<<6)	/* CLKIN Input Divider 00b: Devide by 1. 01b: Divide by 2. 10b: Divide by 4. 11b: Divide by 8. */
#define SI5351_PLLB_SRC		(1u<<3) /* Input Source Select for PLLB. 0..Select the XTAL input as the reference clock for PLLB */
#define SI5351_PLLA_SRC		(1u<<2) /* Input Source Select for PLLA. */
#define SI5351_PLL_INPUT_SOURCE_RESET_VALUE		0x00

/* CLK0 Control */
#define SI5351_CLK0_CONTROL			16u	/* R/W */
#define SI5351_CLK0_PDN		(1u<<7) /* Clock 0 Power Down. */
#define SI5351_MS0_INT		(1u<<6)	/* MultiSynth 0 Integer Mode. 1..MS0 operates in integer mode. */
#define SI5351_MS0_SRC		(1u<<5)	/* MultiSynth Source Select for CLK0 */
#define SI5351_CLK0_INV		(1u<<4) /* Output Clock 0 Invert. */
#define SI5351_CLK0_SRC_1	(1u<<3) /* Output Clock 0 Input Source */
#define SI5351_CLK0_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK0. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK0_SRC		(3u<<2) /* and connects CLK0 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK_SRC_XTAL		(0x00<<2)	/*!< Select the XTAL as the clock source for CLKx */
#define SI5351_CLK_SRC_CLKIN 	(0x01<<2)	/*!< Select the CLKIN as the clock source for CLKx */
#define SI5351_CLK_SRC_RESERVED	(0x02<<2)	/*!< DO NOT Select this option */
#define SI5351_CLK_SRC_MS0		(0x03<<2)	/*!< Select the MulitSynth 0 as the clock source for CLKx */
#define SI5351_CLK0_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK0. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 0 as source for CLK0 */
#define SI5351_CLK0_IDRV_0	(1u<<0) /* CLK0 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK0_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK_2_MA		(0x00)	/*!< 2 mA output rise and fall time / drive strength control */
#define SI5351_CLK_4_MA		(0x01)	/*!< 4 mA output rise and fall time / drive strength control */
#define SI5351_CLK_6_MA		(0x02)	/*!< 6 mA output rise and fall time / drive strength control */
#define SI5351_CLK_8_MA		(0x03)	/*!< 8 mA output rise and fall time / drive strength control */
#define SI5351_CLK0_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK1_CONTROL			17u	/* R/W */
#define SI5351_CLK1_PDN		(1u<<7) /* Clock 1 Power Down. */
#define SI5351_MS1_INT		(1u<<6)	/* MultiSynth 1 Integer Mode. 1..MS1 operates in integer mode. */
#define SI5351_MS1_SRC		(1u<<5)	/* MultiSynth Source Select for CLK1 */
#define SI5351_CLK1_INV		(1u<<4) /* Output Clock 1 Invert. */
#define SI5351_CLK1_SRC_1	(1u<<3) /* Output Clock 1 Input Source */
#define SI5351_CLK1_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK0. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK1_SRC		(3u<<2) /* and connects CLK1 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK1_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK1. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 1 as source for CLK1 */
#define SI5351_CLK1_IDRV_0	(1u<<0) /* CLK1 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK1_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK1_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK2_CONTROL			18u	/* R/W */
#define SI5351_CLK2_PDN		(1u<<7) /* Clock 2 Power Down. */
#define SI5351_MS2_INT		(1u<<6)	/* MultiSynth 2 Integer Mode. 1..MS2 operates in integer mode. */
#define SI5351_MS2_SRC		(1u<<5)	/* MultiSynth Source Select for CLK2 */
#define SI5351_CLK2_INV		(1u<<4) /* Output Clock 2 Invert. */
#define SI5351_CLK2_SRC_1	(1u<<3) /* Output Clock 2 Input Source */
#define SI5351_CLK2_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK2. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK2_SRC		(3u<<2) /* and connects CLK2 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK2_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK2. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 2 as source for CLK2 */
#define SI5351_CLK2_IDRV_0	(1u<<0) /* CLK2 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK2_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK2_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK3_CONTROL			19u	/* R/W */
#define SI5351_CLK3_PDN		(1u<<7) /* Clock 3 Power Down. */
#define SI5351_MS3_INT		(1u<<6)	/* MultiSynth 3 Integer Mode. 1..MS3 operates in integer mode. */
#define SI5351_MS3_SRC		(1u<<5)	/* MultiSynth Source Select for CLK3 */
#define SI5351_CLK3_INV		(1u<<4) /* Output Clock 3 Invert. */
#define SI5351_CLK3_SRC_1	(1u<<3) /* Output Clock 3 Input Source */
#define SI5351_CLK3_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK3. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK3_SRC		(3u<<2) /* and connects CLK3 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK3_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK3. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 3 as source for CLK3 */
#define SI5351_CLK3_IDRV_0	(1u<<0) /* CLK3 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK3_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK3_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK4_CONTROL			20u	/* R/W */
#define SI5351_CLK4_PDN		(1u<<7) /* Clock 4 Power Down. */
#define SI5351_MS4_INT		(1u<<6)	/* MultiSynth 4 Integer Mode. 1..MS4 operates in integer mode. */
#define SI5351_MS4_SRC		(1u<<5)	/* MultiSynth Source Select for CLK4 */
#define SI5351_CLK4_INV		(1u<<4) /* Output Clock 4 Invert. */
#define SI5351_CLK4_SRC_1	(1u<<3) /* Output Clock 4 Input Source */
#define SI5351_CLK4_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK4. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK4_SRC		(3u<<2) /* and connects CLK4 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK4_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK4. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 4 as source for CLK4 */
#define SI5351_CLK4_IDRV_0	(1u<<0) /* CLK4 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK4_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK4_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK5_CONTROL			21u	/* R/W */
#define SI5351_CLK5_PDN		(1u<<7) /* Clock 5 Power Down. */
#define SI5351_MS5_INT		(1u<<6)	/* MultiSynth 5 Integer Mode. 1..MS5 operates in integer mode. */
#define SI5351_MS5_SRC		(1u<<5)	/* MultiSynth Source Select for CLK5 */
#define SI5351_CLK5_INV		(1u<<4) /* Output Clock 5 Invert. */
#define SI5351_CLK5_SRC_1	(1u<<3) /* Output Clock 5 Input Source */
#define SI5351_CLK5_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK5. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK5_SRC		(3u<<2) /* and connects CLK5 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK5_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK5. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 5 as source for CLK5 */
#define SI5351_CLK5_IDRV_0	(1u<<0) /* CLK5 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK5_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK5_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK6_CONTROL			22u	/* R/W */
#define SI5351_CLK6_PDN		(1u<<7) /* Clock 6 Power Down. */
/* #define SI5351_MS6_INT	(1u<<6) */
#define SI5351_FBA_INT		(1u<<6)	/*!< FBA MultiSynth Integer Mode. 1..MSNA operates in integer mode */
#define SI5351_MS6_SRC		(1u<<5)	/* MultiSynth Source Select for CLK6 */
#define SI5351_CLK6_INV		(1u<<4) /* Output Clock 6 Invert. */
#define SI5351_CLK6_SRC_1	(1u<<3) /* Output Clock 6 Input Source */
#define SI5351_CLK6_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK6. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK6_SRC		(3u<<2) /* and connects CLK6 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK6_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK6. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 6 as source for CLK6 */
#define SI5351_CLK6_IDRV_0	(1u<<0) /* CLK6 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK6_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK6_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK7_CONTROL			23u	/* R/W */
#define SI5351_CLK7_PDN		(1u<<7) /* Clock 7 Power Down. */
/* #define SI5351_MS7_INT	(1u<<6)	*/
#define SI5351_FBB_INT		(1u<<6) /*!< FBB Multisynth Integer Mode. 1..MSNB operates in integer mode */
#define SI5351_MS7_SRC		(1u<<5)	/* MultiSynth Source Select for CLK7 */
#define SI5351_CLK7_INV		(1u<<4) /* Output Clock 7 Invert. */
#define SI5351_CLK7_SRC_1	(1u<<3) /* Output Clock 7 Input Source */
#define SI5351_CLK7_SRC_0	(1u<<2) /* 00: Select the XTAL as the clock source for CLK7. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
#define SI5351_CLK7_SRC		(3u<<2) /* and connects CLK7 directly to the oscillator which generates an output freq determined by the XTAL freq. */
#define SI5351_CLK7_IDRV_1	(1u<<1) /* 01: CLKIN as clock source for CLK7. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 7 as source for CLK7 */
#define SI5351_CLK7_IDRV_0	(1u<<0) /* CLK7 Output Rise and Fall time / Drive Strength Control */
#define SI5351_CLK7_IDRV	(3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
#define SI5351_CLK7_CONTROL_RESET_VALUE			0x00

#define SI5351_CLK3_0_DISABLE_STATE	24u /* R/W */
#define SI5351_CLK3_DIS_STATE_1	(1u<<7)	/* Clock x Disable State 00: CLKx is set to a LOW state when disabled, */
#define SI5351_CLK3_DIS_STATE_0	(1u<<6)	/*  01: CLKx is set to a HIGH state when disabled, */
#define SI5351_CLK3_DIS_STATE	(3u<<6) /*  10: CLKx is set to a HIGH IMPEDANCE state when disabled, */
#define SI5351_CLK2_DIS_STATE_1 (1u<<5) /*  11: CLKx is NEVER DISABLED */
#define SI5351_CLK2_DIS_STATE_0	(1u<<4)
#define SI5351_CLK2_DIS_STATE	(3u<<4)
#define SI5351_CLK1_DIS_STATE_1 (1u<<3)
#define SI5351_CLK1_DIS_STATE_0	(1u<<2)
#define SI5351_CLK1_DIS_STATE	(3u<<2)
#define SI5351_CLK0_DIS_STATE_1 (1u<<1)
#define SI5351_CLK0_DIS_STATE_0	(1u<<0)
#define SI5351_CLK0_DIS_STATE	(3u<<0)
#define SI5351_CLK3_0_DISABLE_STATE_RESET_VALUE	0x00

#define SI5351_CLK7_4_DISABLE_STATE	25u /* R/W */
#define SI5351_CLK7_DIS_STATE_1	(1u<<7)	/* Clock x Disable State 00: CLKx is set to a LOW state when disabled, */
#define SI5351_CLK7_DIS_STATE_0	(1u<<6)	/*  01: CLKx is set to a HIGH state when disabled, */
#define SI5351_CLK7_DIS_STATE	(3u<<6) /*  10: CLKx is set to a HIGH IMPEDANCE state when disabled, */
#define SI5351_CLK6_DIS_STATE_1 (1u<<5) /*  11: CLKx is NEVER DISABLED */
#define SI5351_CLK6_DIS_STATE_0	(1u<<4)
#define SI5351_CLK6_DIS_STATE	(3u<<4)
#define SI5351_CLK5_DIS_STATE_1 (1u<<3)
#define SI5351_CLK5_DIS_STATE_0	(1u<<2)
#define SI5351_CLK5_DIS_STATE	(3u<<2)
#define SI5351_CLK4_DIS_STATE_1 (1u<<1)
#define SI5351_CLK4_DIS_STATE_0	(1u<<0)
#define SI5351_CLK4_DIS_STATE	(3u<<0)
#define SI5351_CLK4_0_DISABLE_STATE_RESET_VALUE	0x00

/* Multisynth NA Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the PLLA Feedback Multisynth Divider. */

#define SI5351_MULTISYNTH_NA_PARAMETER_3_HI	26u /* R/W */
#define MSNA_P3_15		(1u<<7)
#define MSNA_P3_14		(1u<<6)
#define MSNA_P3_13		(1u<<5)
#define MSNA_P3_12		(1u<<4)
#define MSNA_P3_11		(1u<<3)
#define MSNA_P3_10		(1u<<2)
#define MSNA_P3_9		(1u<<1)
#define MSNA_P3_8		(1u<<0)
#define MSNA_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH_NA_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH_NA_PARAMETER_3_LO	27u /* R/W */
#define MSNA_P3_7		(1u<<7)
#define MSNA_P3_6		(1u<<6)
#define MSNA_P3_5		(1u<<5)
#define MSNA_P3_4		(1u<<4)
#define MSNA_P3_3		(1u<<3)
#define MSNA_P3_2		(1u<<2)
#define MSNA_P3_1		(1u<<1)
#define MSNA_P3_0		(1u<<0)
#define MSNA_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NA_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth NA Parameter 1.
This 18-bit number is an encoded representation of the integer part of the PLLA
Feedback Multisynth divider. */

#define SI5351_MULTISYNTH_NA_PARAMETER_1_HIHI	28u /* R/W */
#define MSNA_P1_17		(1u<<1)
#define MSNA_P1_16		(1u<<0)
#define MSNA_P1_17_16	(3u<<0)

#define SI5351_MULTISYNTH_NA_PARAMETER_1_HI	29u /* R/W */
#define MSNA_P1_15		(1u<<7)
#define MSNA_P1_14		(1u<<6)
#define MSNA_P1_13		(1u<<5)
#define MSNA_P1_12		(1u<<4)
#define MSNA_P1_11		(1u<<3)
#define MSNA_P1_10		(1u<<2)
#define MSNA_P1_9		(1u<<1)
#define MSNA_P1_8		(1u<<0)
#define MSNA_P1_15_8	(0xFF)

#define SI5351_MULTISYNTH_NA_PARAMETER_1_LO	30u /* R/W */
#define MSNA_P1_7		(1u<<7)
#define MSNA_P1_6		(1u<<6)
#define MSNA_P1_5		(1u<<5)
#define MSNA_P1_4		(1u<<4)
#define MSNA_P1_3		(1u<<3)
#define MSNA_P1_2		(1u<<2)
#define MSNA_P1_1		(1u<<1)
#define MSNA_P1_0		(1u<<0)
#define MSNA_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NA_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH_NA_PARAMETER_3_2_HIHI	31u	/* R/W */
#define MSNA_P3_19		(1u<<7)
#define MSNA_P3_18		(1u<<6)
#define MSNA_P3_17		(1u<<5)
#define MSNA_P3_16		(1u<<4)
#define MSNA_P3_19_16	(7u<<4)
#define MSNA_P2_19		(1u<<3)
#define MSNA_P2_18		(1u<<2)
#define MSNA_P2_17		(1u<<1)
#define MSNA_P2_16		(1u<<0)
#define MSNA_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH_NA_PARAMETER_2_HI	32u /* R/W */
#define MSNA_P2_15		(1u<<7)
#define MSNA_P2_14		(1u<<6)
#define MSNA_P2_13		(1u<<5)
#define MSNA_P2_12		(1u<<4)
#define MSNA_P2_11		(1u<<3)
#define MSNA_P2_10		(1u<<2)
#define MSNA_P2_9		(1u<<1)
#define MSNA_P2_8		(1u<<0)
#define MSNA_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH_NA_PARAMETER_2_LO	33u /* R/W */
#define MSNA_P2_7		(1u<<7)
#define MSNA_P2_6		(1u<<6)
#define MSNA_P2_5		(1u<<5)
#define MSNA_P2_4		(1u<<4)
#define MSNA_P2_3		(1u<<3)
#define MSNA_P2_2		(1u<<2)
#define MSNA_P2_1		(1u<<1)
#define MSNA_P2_0		(1u<<0)
#define MSNA_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NA_PARAMETER_2_LO_RESET_VALUE	0xXX */

/* Multisynth NB Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the PLLB Feedback Multisynth divider. */

#define SI5351_MULTISYNTH_NB_PARAMETER_3_HI	34u /* R/W */
#define MSNB_P3_15		(1u<<7)
#define MSNB_P3_14		(1u<<6)
#define MSNB_P3_13		(1u<<5)
#define MSNB_P3_12		(1u<<4)
#define MSNB_P3_11		(1u<<3)
#define MSNB_P3_10		(1u<<2)
#define MSNB_P3_9		(1u<<1)
#define MSNB_P3_8		(1u<<0)
#define MSNB_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH_NB_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH_NB_PARAMETER_3_LO	35u /* R/W */
#define MSNB_P3_7		(1u<<7)
#define MSNB_P3_6		(1u<<6)
#define MSNB_P3_5		(1u<<5)
#define MSNB_P3_4		(1u<<4)
#define MSNB_P3_3		(1u<<3)
#define MSNB_P3_2		(1u<<2)
#define MSNB_P3_1		(1u<<1)
#define MSNB_P3_0		(1u<<0)
#define MSNB_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NB_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth NB Parameter 1.
This 18-bit number is an encoded representation of the integer part of the PLLA
Feedback Multisynth divider. */

#define SI5351_MULTISYNTH_NB_PARAMETER_1_HIHI	36u /* R/W */
#define MSNB_P1_17		(1u<<1)
#define MSNB_P1_16		(1u<<0)
#define MSNB_P1_17_16	(3u<<0)

#define SI5351_MULTISYNTH_NB_PARAMETER_1_HI	37u /* R/W */
#define MSNB_P1_15		(1u<<7)
#define MSNB_P1_14		(1u<<6)
#define MSNB_P1_13		(1u<<5)
#define MSNB_P1_12		(1u<<4)
#define MSNB_P1_11		(1u<<3)
#define MSNB_P1_10		(1u<<2)
#define MSNB_P1_9		(1u<<1)
#define MSNB_P1_8		(1u<<0)
#define MSNB_P1_15_8	(0xFF)

#define SI5351_MULTISYNTH_NB_PARAMETER_1_LO	38u /* R/W */
#define MSNB_P1_7		(1u<<7)
#define MSNB_P1_6		(1u<<6)
#define MSNB_P1_5		(1u<<5)
#define MSNB_P1_4		(1u<<4)
#define MSNB_P1_3		(1u<<3)
#define MSNB_P1_2		(1u<<2)
#define MSNB_P1_1		(1u<<1)
#define MSNB_P1_0		(1u<<0)
#define MSNB_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NB_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH_NB_PARAMETER_3_2_HIHI	39u	/* R/W */
#define MSNB_P3_19		(1u<<7)
#define MSNB_P3_18		(1u<<6)
#define MSNB_P3_17		(1u<<5)
#define MSNB_P3_16		(1u<<4)
#define MSNB_P3_19_16	(7u<<4)
#define MSNB_P2_19		(1u<<3)
#define MSNB_P2_18		(1u<<2)
#define MSNB_P2_17		(1u<<1)
#define MSNB_P2_16		(1u<<0)
#define MSNB_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH_NB_PARAMETER_2_HI	40u /* R/W */
#define MSNB_P2_15		(1u<<7)
#define MSNB_P2_14		(1u<<6)
#define MSNB_P2_13		(1u<<5)
#define MSNB_P2_12		(1u<<4)
#define MSNB_P2_11		(1u<<3)
#define MSNB_P2_10		(1u<<2)
#define MSNB_P2_9		(1u<<1)
#define MSNB_P2_8		(1u<<0)
#define MSNB_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH_NB_PARAMETER_2_LO	41u /* R/W */
#define MSNB_P2_7		(1u<<7)
#define MSNB_P2_6		(1u<<6)
#define MSNB_P2_5		(1u<<5)
#define MSNB_P2_4		(1u<<4)
#define MSNB_P2_3		(1u<<3)
#define MSNB_P2_2		(1u<<2)
#define MSNB_P2_1		(1u<<1)
#define MSNB_P2_0		(1u<<0)
#define MSNB_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH_NB_PARAMETER_2_LO_RESET_VALUE	0xXX */

/* Multisynth0 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth0 Divider. */

#define SI5351_MULTISYNTH0_PARAMETER_3_HI	42u /* R/W */
#define MS0_P3_15		(1u<<7)
#define MS0_P3_14		(1u<<6)
#define MS0_P3_13		(1u<<5)
#define MS0_P3_12		(1u<<4)
#define MS0_P3_11		(1u<<3)
#define MS0_P3_10		(1u<<2)
#define MS0_P3_9		(1u<<1)
#define MS0_P3_8		(1u<<0)
#define MS0_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH0_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH0_PARAMETER_3_LO	43u /* R/W */
#define MS0_P3_7		(1u<<7)
#define MS0_P3_6		(1u<<6)
#define MS0_P3_5		(1u<<5)
#define MS0_P3_4		(1u<<4)
#define MS0_P3_3		(1u<<3)
#define MS0_P3_2		(1u<<2)
#define MS0_P3_1		(1u<<1)
#define MS0_P3_0		(1u<<0)
#define MS0_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH0_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth0 Parameters R0 Output Divider, MS0 Divide by 4 Enable,
 * Multisynth0 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth0 divider. */

#define SI5351_MULTISYNTH0_PARAMETER_DIV	44u /* R/W */
#define R0_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R0_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R0_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R0_DIV			(7u<<4)
#define MS0_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS0_DIVBY4_0	(1u<<2)
#define MS0_DIVBY4		(3u<<2)
#define MS0_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS0_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS0_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH0_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH0_PARAMETER_1_HI	45u /* R/W */
#define MS0_P1_15		(1u<<7)
#define MS0_P1_14		(1u<<6)
#define MS0_P1_13		(1u<<5)
#define MS0_P1_12		(1u<<4)
#define MS0_P1_11		(1u<<3)
#define MS0_P1_10		(1u<<2)
#define MS0_P1_9		(1u<<1)
#define MS0_P1_8		(1u<<0)
#define MS0_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH0_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH0_PARAMETER_1_LO	46u /* R/W */
#define MS0_P1_7		(1u<<7)
#define MS0_P1_6		(1u<<6)
#define MS0_P1_5		(1u<<5)
#define MS0_P1_4		(1u<<4)
#define MS0_P1_3		(1u<<3)
#define MS0_P1_2		(1u<<2)
#define MS0_P1_1		(1u<<1)
#define MS0_P1_0		(1u<<0)
#define MS0_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH0_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH0_PARAMETER_3_2_HIHI	47u	/* R/W */
#define MS0_P3_19		(1u<<7)
#define MS0_P3_18		(1u<<6)
#define MS0_P3_17		(1u<<5)
#define MS0_P3_16		(1u<<4)
#define MS0_P3_19_16	(7u<<4)
#define MS0_P2_19		(1u<<3)
#define MS0_P2_18		(1u<<2)
#define MS0_P2_17		(1u<<1)
#define MS0_P2_16		(1u<<0)
#define MS0_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH0_PARAMETER_2_HI	48u /* R/W */
#define MS0_P2_15		(1u<<7)
#define MS0_P2_14		(1u<<6)
#define MS0_P2_13		(1u<<5)
#define MS0_P2_12		(1u<<4)
#define MS0_P2_11		(1u<<3)
#define MS0_P2_10		(1u<<2)
#define MS0_P2_9		(1u<<1)
#define MS0_P2_8		(1u<<0)
#define MS0_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH0_PARAMETER_2_LO	49u /* R/W */
#define MS0_P2_7		(1u<<7)
#define MS0_P2_6		(1u<<6)
#define MS0_P2_5		(1u<<5)
#define MS0_P2_4		(1u<<4)
#define MS0_P2_3		(1u<<3)
#define MS0_P2_2		(1u<<2)
#define MS0_P2_1		(1u<<1)
#define MS0_P2_0		(1u<<0)
#define MS0_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH0_PARAMETER_2_LO_RESET_VALUE	0xXX */

/* Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth1 Divider. */

#define SI5351_MULTISYNTH1_PARAMETER_3_HI	50u /* R/W */
#define MS1_P3_15		(1u<<7)
#define MS1_P3_14		(1u<<6)
#define MS1_P3_13		(1u<<5)
#define MS1_P3_12		(1u<<4)
#define MS1_P3_11		(1u<<3)
#define MS1_P3_10		(1u<<2)
#define MS1_P3_9		(1u<<1)
#define MS1_P3_8		(1u<<0)
#define MS1_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH1_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH1_PARAMETER_3_LO	51u /* R/W */
#define MS1_P3_7		(1u<<7)
#define MS1_P3_6		(1u<<6)
#define MS1_P3_5		(1u<<5)
#define MS1_P3_4		(1u<<4)
#define MS1_P3_3		(1u<<3)
#define MS1_P3_2		(1u<<2)
#define MS1_P3_1		(1u<<1)
#define MS1_P3_0		(1u<<0)
#define MS1_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH1_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth1 Parameters R1 Output Divider, MS1 Divide by 4 Enable,
 * Multisynth1 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth1 divider. */

#define SI5351_MULTISYNTH1_PARAMETER_DIV	52u /* R/W */
#define R1_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R1_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R1_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R1_DIV			(7u<<4)
#define MS1_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS1_DIVBY4_0	(1u<<2)
#define MS1_DIVBY4		(3u<<2)
#define MS1_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS1_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS1_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH1_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH1_PARAMETER_1_HI	53u /* R/W */
#define MS1_P1_15		(1u<<7)
#define MS1_P1_14		(1u<<6)
#define MS1_P1_13		(1u<<5)
#define MS1_P1_12		(1u<<4)
#define MS1_P1_11		(1u<<3)
#define MS1_P1_10		(1u<<2)
#define MS1_P1_9		(1u<<1)
#define MS1_P1_8		(1u<<0)
#define MS1_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH1_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH1_PARAMETER_1_LO	54u /* R/W */
#define MS1_P1_7		(1u<<7)
#define MS1_P1_6		(1u<<6)
#define MS1_P1_5		(1u<<5)
#define MS1_P1_4		(1u<<4)
#define MS1_P1_3		(1u<<3)
#define MS1_P1_2		(1u<<2)
#define MS1_P1_1		(1u<<1)
#define MS1_P1_0		(1u<<0)
#define MS1_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH1_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH1_PARAMETER_3_2_HIHI	55u	/* R/W */
#define MS1_P3_19		(1u<<7)
#define MS1_P3_18		(1u<<6)
#define MS1_P3_17		(1u<<5)
#define MS1_P3_16		(1u<<4)
#define MS1_P3_19_16	(7u<<4)
#define MS1_P2_19		(1u<<3)
#define MS1_P2_18		(1u<<2)
#define MS1_P2_17		(1u<<1)
#define MS1_P2_16		(1u<<0)
#define MS1_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH1_PARAMETER_2_HI	56u /* R/W */
#define MS1_P2_15		(1u<<7)
#define MS1_P2_14		(1u<<6)
#define MS1_P2_13		(1u<<5)
#define MS1_P2_12		(1u<<4)
#define MS1_P2_11		(1u<<3)
#define MS1_P2_10		(1u<<2)
#define MS1_P2_9		(1u<<1)
#define MS1_P2_8		(1u<<0)
#define MS1_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH1_PARAMETER_2_LO	57u /* R/W */
#define MS1_P2_7		(1u<<7)
#define MS1_P2_6		(1u<<6)
#define MS1_P2_5		(1u<<5)
#define MS1_P2_4		(1u<<4)
#define MS1_P2_3		(1u<<3)
#define MS1_P2_2		(1u<<2)
#define MS1_P2_1		(1u<<1)
#define MS1_P2_0		(1u<<0)
#define MS1_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH1_PARAMETER_2_LO_RESET_VALUE	0xXX */


/* Multisynth2 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth2 Divider. */

#define SI5351_MULTISYNTH2_PARAMETER_3_HI	58u /* R/W */
#define MS2_P3_15		(1u<<7)
#define MS2_P3_14		(1u<<6)
#define MS2_P3_13		(1u<<5)
#define MS2_P3_12		(1u<<4)
#define MS2_P3_11		(1u<<3)
#define MS2_P3_10		(1u<<2)
#define MS2_P3_9		(1u<<1)
#define MS2_P3_8		(1u<<0)
#define MS2_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH2_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH2_PARAMETER_3_LO	59u /* R/W */
#define MS2_P3_7		(1u<<7)
#define MS2_P3_6		(1u<<6)
#define MS2_P3_5		(1u<<5)
#define MS2_P3_4		(1u<<4)
#define MS2_P3_3		(1u<<3)
#define MS2_P3_2		(1u<<2)
#define MS2_P3_1		(1u<<1)
#define MS2_P3_0		(1u<<0)
#define MS2_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH2_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth2 Parameters R2 Output Divider, MS2 Divide by 4 Enable,
 * Multisynth2 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth2 divider. */

#define SI5351_MULTISYNTH2_PARAMETER_DIV	60u /* R/W */
#define R2_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R2_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R2_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R2_DIV			(7u<<4)
#define MS2_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS2_DIVBY4_0	(1u<<2)
#define MS2_DIVBY4		(3u<<2)
#define MS2_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS2_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS2_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH2_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH2_PARAMETER_1_HI	61u /* R/W */
#define MS2_P1_15		(1u<<7)
#define MS2_P1_14		(1u<<6)
#define MS2_P1_13		(1u<<5)
#define MS2_P1_12		(1u<<4)
#define MS2_P1_11		(1u<<3)
#define MS2_P1_10		(1u<<2)
#define MS2_P1_9		(1u<<1)
#define MS2_P1_8		(1u<<0)
#define MS2_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH2_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH2_PARAMETER_1_LO	62u /* R/W */
#define MS2_P1_7		(1u<<7)
#define MS2_P1_6		(1u<<6)
#define MS2_P1_5		(1u<<5)
#define MS2_P1_4		(1u<<4)
#define MS2_P1_3		(1u<<3)
#define MS2_P1_2		(1u<<2)
#define MS2_P1_1		(1u<<1)
#define MS2_P1_0		(1u<<0)
#define MS2_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH2_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH2_PARAMETER_3_2_HIHI	63u	/* R/W */
#define MS2_P3_19		(1u<<7)
#define MS2_P3_18		(1u<<6)
#define MS2_P3_17		(1u<<5)
#define MS2_P3_16		(1u<<4)
#define MS2_P3_19_16	(7u<<4)
#define MS2_P2_19		(1u<<3)
#define MS2_P2_18		(1u<<2)
#define MS2_P2_17		(1u<<1)
#define MS2_P2_16		(1u<<0)
#define MS2_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH2_PARAMETER_2_HI	64u /* R/W */
#define MS2_P2_15		(1u<<7)
#define MS2_P2_14		(1u<<6)
#define MS2_P2_13		(1u<<5)
#define MS2_P2_12		(1u<<4)
#define MS2_P2_11		(1u<<3)
#define MS2_P2_10		(1u<<2)
#define MS2_P2_9		(1u<<1)
#define MS2_P2_8		(1u<<0)
#define MS2_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH2_PARAMETER_2_LO	65u /* R/W */
#define MS2_P2_7		(1u<<7)
#define MS2_P2_6		(1u<<6)
#define MS2_P2_5		(1u<<5)
#define MS2_P2_4		(1u<<4)
#define MS2_P2_3		(1u<<3)
#define MS2_P2_2		(1u<<2)
#define MS2_P2_1		(1u<<1)
#define MS2_P2_0		(1u<<0)
#define MS2_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH2_PARAMETER_2_LO_RESET_VALUE	0xXX */


/* Multisynth3 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth3 Divider. */

#define SI5351_MULTISYNTH3_PARAMETER_3_HI	66u /* R/W */
#define MS3_P3_15		(1u<<7)
#define MS3_P3_14		(1u<<6)
#define MS3_P3_13		(1u<<5)
#define MS3_P3_12		(1u<<4)
#define MS3_P3_11		(1u<<3)
#define MS3_P3_10		(1u<<2)
#define MS3_P3_9		(1u<<1)
#define MS3_P3_8		(1u<<0)
#define MS3_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH3_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH3_PARAMETER_3_LO	67u /* R/W */
#define MS3_P3_7		(1u<<7)
#define MS3_P3_6		(1u<<6)
#define MS3_P3_5		(1u<<5)
#define MS3_P3_4		(1u<<4)
#define MS3_P3_3		(1u<<3)
#define MS3_P3_2		(1u<<2)
#define MS3_P3_1		(1u<<1)
#define MS3_P3_0		(1u<<0)
#define MS3_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH3_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth3 Parameters R3 Output Divider, MS3 Divide by 4 Enable,
 * Multisynth3 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth3 divider. */

#define SI5351_MULTISYNTH3_PARAMETER_DIV	68u /* R/W */
#define R3_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R3_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R3_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R3_DIV			(7u<<4)
#define MS3_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS3_DIVBY4_0	(1u<<2)
#define MS3_DIVBY4		(3u<<2)
#define MS3_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS3_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS3_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH3_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH3_PARAMETER_1_HI	69u /* R/W */
#define MS3_P1_15		(1u<<7)
#define MS3_P1_14		(1u<<6)
#define MS3_P1_13		(1u<<5)
#define MS3_P1_12		(1u<<4)
#define MS3_P1_11		(1u<<3)
#define MS3_P1_10		(1u<<2)
#define MS3_P1_9		(1u<<1)
#define MS3_P1_8		(1u<<0)
#define MS3_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH3_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH3_PARAMETER_1_LO	70u /* R/W */
#define MS3_P1_7		(1u<<7)
#define MS3_P1_6		(1u<<6)
#define MS3_P1_5		(1u<<5)
#define MS3_P1_4		(1u<<4)
#define MS3_P1_3		(1u<<3)
#define MS3_P1_2		(1u<<2)
#define MS3_P1_1		(1u<<1)
#define MS3_P1_0		(1u<<0)
#define MS3_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH3_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH3_PARAMETER_3_2_HIHI	71u	/* R/W */
#define MS3_P3_19		(1u<<7)
#define MS3_P3_18		(1u<<6)
#define MS3_P3_17		(1u<<5)
#define MS3_P3_16		(1u<<4)
#define MS3_P3_19_16	(7u<<4)
#define MS3_P2_19		(1u<<3)
#define MS3_P2_18		(1u<<2)
#define MS3_P2_17		(1u<<1)
#define MS3_P2_16		(1u<<0)
#define MS3_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH3_PARAMETER_2_HI	72u /* R/W */
#define MS3_P2_15		(1u<<7)
#define MS3_P2_14		(1u<<6)
#define MS3_P2_13		(1u<<5)
#define MS3_P2_12		(1u<<4)
#define MS3_P2_11		(1u<<3)
#define MS3_P2_10		(1u<<2)
#define MS3_P2_9		(1u<<1)
#define MS3_P2_8		(1u<<0)
#define MS3_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH3_PARAMETER_2_LO	73u /* R/W */
#define MS3_P2_7		(1u<<7)
#define MS3_P2_6		(1u<<6)
#define MS3_P2_5		(1u<<5)
#define MS3_P2_4		(1u<<4)
#define MS3_P2_3		(1u<<3)
#define MS3_P2_2		(1u<<2)
#define MS3_P2_1		(1u<<1)
#define MS3_P2_0		(1u<<0)
#define MS3_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH3_PARAMETER_2_LO_RESET_VALUE	0xXX */


/* MULTISYNTH5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth4 Divider. */

#define SI5351_MULTISYNTH4_PARAMETER_3_HI	74u /* R/W */
#define MS4_P3_15		(1u<<7)
#define MS4_P3_14		(1u<<6)
#define MS4_P3_13		(1u<<5)
#define MS4_P3_12		(1u<<4)
#define MS4_P3_11		(1u<<3)
#define MS4_P3_10		(1u<<2)
#define MS4_P3_9		(1u<<1)
#define MS4_P3_8		(1u<<0)
#define MS4_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH4_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH4_PARAMETER_3_LO	75u /* R/W */
#define MS4_P3_7		(1u<<7)
#define MS4_P3_6		(1u<<6)
#define MS4_P3_5		(1u<<5)
#define MS4_P3_4		(1u<<4)
#define MS4_P3_3		(1u<<3)
#define MS4_P3_2		(1u<<2)
#define MS4_P3_1		(1u<<1)
#define MS4_P3_0		(1u<<0)
#define MS4_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH4_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth4 Parameters R3 Output Divider, MS4 Divide by 4 Enable,
 * Multisynth4 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth3 divider. */

#define SI5351_MULTISYNTH4_PARAMETER_DIV	76u /* R/W */
#define R3_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R3_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R3_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R3_DIV			(7u<<4)
#define MS4_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS4_DIVBY4_0	(1u<<2)
#define MS4_DIVBY4		(3u<<2)
#define MS4_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS4_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS4_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH4_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH4_PARAMETER_1_HI	77u /* R/W */
#define MS4_P1_15		(1u<<7)
#define MS4_P1_14		(1u<<6)
#define MS4_P1_13		(1u<<5)
#define MS4_P1_12		(1u<<4)
#define MS4_P1_11		(1u<<3)
#define MS4_P1_10		(1u<<2)
#define MS4_P1_9		(1u<<1)
#define MS4_P1_8		(1u<<0)
#define MS4_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH4_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH4_PARAMETER_1_LO	78u /* R/W */
#define MS4_P1_7		(1u<<7)
#define MS4_P1_6		(1u<<6)
#define MS4_P1_5		(1u<<5)
#define MS4_P1_4		(1u<<4)
#define MS4_P1_3		(1u<<3)
#define MS4_P1_2		(1u<<2)
#define MS4_P1_1		(1u<<1)
#define MS4_P1_0		(1u<<0)
#define MS4_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH4_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH4_PARAMETER_3_2_HIHI	79u	/* R/W */
#define MS4_P3_19		(1u<<7)
#define MS4_P3_18		(1u<<6)
#define MS4_P3_17		(1u<<5)
#define MS4_P3_16		(1u<<4)
#define MS4_P3_19_16	(7u<<4)
#define MS4_P2_19		(1u<<3)
#define MS4_P2_18		(1u<<2)
#define MS4_P2_17		(1u<<1)
#define MS4_P2_16		(1u<<0)
#define MS4_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH4_PARAMETER_2_HI	80u /* R/W */
#define MS4_P2_15		(1u<<7)
#define MS4_P2_14		(1u<<6)
#define MS4_P2_13		(1u<<5)
#define MS4_P2_12		(1u<<4)
#define MS4_P2_11		(1u<<3)
#define MS4_P2_10		(1u<<2)
#define MS4_P2_9		(1u<<1)
#define MS4_P2_8		(1u<<0)
#define MS4_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH4_PARAMETER_2_LO	81u /* R/W */
#define MS4_P2_7		(1u<<7)
#define MS4_P2_6		(1u<<6)
#define MS4_P2_5		(1u<<5)
#define MS4_P2_4		(1u<<4)
#define MS4_P2_3		(1u<<3)
#define MS4_P2_2		(1u<<2)
#define MS4_P2_1		(1u<<1)
#define MS4_P2_0		(1u<<0)
#define MS4_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH4_PARAMETER_2_LO_RESET_VALUE	0xXX */


/* Multisynth5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth5 Divider. */

#define SI5351_MULTISYNTH5_PARAMETER_3_HI	82u /* R/W */
#define MS5_P3_15		(1u<<7)
#define MS5_P3_14		(1u<<6)
#define MS5_P3_13		(1u<<5)
#define MS5_P3_12		(1u<<4)
#define MS5_P3_11		(1u<<3)
#define MS5_P3_10		(1u<<2)
#define MS5_P3_9		(1u<<1)
#define MS5_P3_8		(1u<<0)
#define MS5_P3_15_8	(0xFF)
/* #define SI5351_MULTISYNTH5_PARAMETER_3_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH5_PARAMETER_3_LO	83u /* R/W */
#define MS5_P3_7		(1u<<7)
#define MS5_P3_6		(1u<<6)
#define MS5_P3_5		(1u<<5)
#define MS5_P3_4		(1u<<4)
#define MS5_P3_3		(1u<<3)
#define MS5_P3_2		(1u<<2)
#define MS5_P3_1		(1u<<1)
#define MS5_P3_0		(1u<<0)
#define MS5_P3_7_0		(0xFF)
/* #define SI5351_MULTISYNTH5_PARAMETER_3_LO_RESET_VALUE	0xXX */

/* Multisynth5 Parameters R3 Output Divider, MS5 Divide by 4 Enable,
 * Multisynth5 Parameter 1
This 18-bit number is an encoded representation of the integer part of the Multi-
Synth3 divider. */

#define SI5351_MULTISYNTH5_PARAMETER_DIV	84u /* R/W */
#define R3_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R3_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R3_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R3_DIV			(7u<<4)
#define MS5_DIVBY4_1	(1u<<3)	/* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */
#define MS5_DIVBY4_0	(1u<<2)
#define MS5_DIVBY4		(3u<<2)
#define MS5_P1_17		(1u<<1)	/* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */
#define MS5_P1_16		(1u<<0)	/* of the integer part of the Multisynth0 divider */
#define MS5_P1_17_16	(3u<<0)
/* #define SI5351_MULTISYNTH5_PARAMETER_DIV_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH5_PARAMETER_1_HI	85u /* R/W */
#define MS5_P1_15		(1u<<7)
#define MS5_P1_14		(1u<<6)
#define MS5_P1_13		(1u<<5)
#define MS5_P1_12		(1u<<4)
#define MS5_P1_11		(1u<<3)
#define MS5_P1_10		(1u<<2)
#define MS5_P1_9		(1u<<1)
#define MS5_P1_8		(1u<<0)
#define MS5_P1_15_8	(0xFF)
/* #define SI5351_MULTISYNTH5_PARAMETER_1_HI_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH5_PARAMETER_1_LO	86u /* R/W */
#define MS5_P1_7		(1u<<7)
#define MS5_P1_6		(1u<<6)
#define MS5_P1_5		(1u<<5)
#define MS5_P1_4		(1u<<4)
#define MS5_P1_3		(1u<<3)
#define MS5_P1_2		(1u<<2)
#define MS5_P1_1		(1u<<1)
#define MS5_P1_0		(1u<<0)
#define MS5_P1_7_0		(0xFF)
/* #define SI5351_MULTISYNTH5_PARAMETER_1_LO_RESET_VALUE	0xXX */

#define SI5351_MULTISYNTH5_PARAMETER_3_2_HIHI	87u	/* R/W */
#define MS5_P3_19		(1u<<7)
#define MS5_P3_18		(1u<<6)
#define MS5_P3_17		(1u<<5)
#define MS5_P3_16		(1u<<4)
#define MS5_P3_19_16	(7u<<4)
#define MS5_P2_19		(1u<<3)
#define MS5_P2_18		(1u<<2)
#define MS5_P2_17		(1u<<1)
#define MS5_P2_16		(1u<<0)
#define MS5_P2_19_16	(7u<<0)

#define SI5351_MULTISYNTH5_PARAMETER_2_HI	88u /* R/W */
#define MS5_P2_15		(1u<<7)
#define MS5_P2_14		(1u<<6)
#define MS5_P2_13		(1u<<5)
#define MS5_P2_12		(1u<<4)
#define MS5_P2_11		(1u<<3)
#define MS5_P2_10		(1u<<2)
#define MS5_P2_9		(1u<<1)
#define MS5_P2_8		(1u<<0)
#define MS5_P2_15_8	(0xFF)

#define SI5351_MULTISYNTH5_PARAMETER_2_LO	89u /* R/W */
#define MS5_P2_7		(1u<<7)
#define MS5_P2_6		(1u<<6)
#define MS5_P2_5		(1u<<5)
#define MS5_P2_4		(1u<<4)
#define MS5_P2_3		(1u<<3)
#define MS5_P2_2		(1u<<2)
#define MS5_P2_1		(1u<<1)
#define MS5_P2_0		(1u<<0)
#define MS5_P2_7_0		(0xFF)
/* #define SI5351_MULTISYNTH5_PARAMETER_2_LO_RESET_VALUE	0xXX */


/* Multisynth6 Parameter 1.
This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be
even integers greater than or equal to 6. All other divide values are invalid. */

#define SI5351_MULTISYNTH6_PARAMETER_1	90u /* R/W */
#define MS6_P1_7		(1u<<7)
#define MS6_P1_6		(1u<<6)
#define MS6_P1_5		(1u<<5)
#define MS6_P1_4		(1u<<4)
#define MS6_P1_3		(1u<<3)
#define MS6_P1_2		(1u<<2)
#define MS6_P1_1		(1u<<1)
#define MS6_P1_0		(1u<<0)
#define MS6_P1			(0xFF)
/* #define SI5351_MULTISYNTH6_PARAMETER_1_RESET_VALUE	0xXX */


/* Multisynth7 Parameter 1.
This 8-bit number is the Multisynth7 divide ratio. Multisynth7 divide ratio can only be
even integers greater than or equal to 6. All other divide values are invalid. */

#define SI5351_MULTISYNTH7_PARAMETER_1	91u /* R/W */
#define MS7_P1_7		(1u<<7)
#define MS7_P1_6		(1u<<6)
#define MS7_P1_5		(1u<<5)
#define MS7_P1_4		(1u<<4)
#define MS7_P1_3		(1u<<3)
#define MS7_P1_2		(1u<<2)
#define MS7_P1_1		(1u<<1)
#define MS7_P1_0		(1u<<0)
#define MS7_P1			(0xFF)
/* #define SI5351_MULTISYNTH7_PARAMETER_1_RESET_VALUE	0xXX */

#define SI5351_CLOCK_6_7_OUTPUT_DEVIDER	92u	/* R/W */
#define R7_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R7_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R7_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R7_DIV			(7u<<4)
#define R6_DIV_2		(1u<<6)	/* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */
#define R6_DIV_1		(1u<<5)	/* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */
#define R6_DIV_0		(1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R6_DIV			(7u<<4)

/* Spread Spectrum Parameters
 * Registers 149 upto 161
 */

/* VCXO Parameters
 * Registers 162 upto 164
 */

/* CLK0 Initial Phase Offset
 * CLK0_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK0_INITIAL_PHASE_OFFSET	165u /* R/W */
#define CLKx_PHOFF_RESERVED	(0u<<7)	/* 0b: Only write 0 to this bit */
#define CLKx_PHOFF_6	(1u<<6)
#define CLKx_PHOFF_5	(1u<<5)
#define CLKx_PHOFF_4	(1u<<4)
#define CLKx_PHOFF_3	(1u<<3)
#define CLKx_PHOFF_2	(1u<<2)
#define CLKx_PHOFF_1	(1u<<1)
#define CLKx_PHOFF_0	(1u<<0)
#define CLKx_PHOFF		(0x7F)
#define CLK0_PHOFF		CLKx_PHOFF

/* CLK1 Initial Phase Offset
 * CLK1_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK1_INITIAL_PHASE_OFFSET	166u /* R/W */
#define CLK1_PHOFF		CLKx_PHOFF

/* CLK2 Initial Phase Offset
 * CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK2_INITIAL_PHASE_OFFSET	167u /* R/W */
#define CLK2_PHOFF		CLKx_PHOFF

/* CLK2 Initial Phase Offset
 * CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK3_INITIAL_PHASE_OFFSET	168u /* R/W */
#define CLK3_PHOFF		CLKx_PHOFF

/* CLK3 Initial Phase Offset
 * CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK4_INITIAL_PHASE_OFFSET	169u /* R/W */
#define CLK4_PHOFF		CLKx_PHOFF

/* CLK4 Initial Phase Offset
 * CLK4_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
 * Tvco is the period of the VCO/PLL associated with this output.
 */
#define SI5351_CLK5_INITIAL_PHASE_OFFSET	170u /* R/W */
#define CLK5_PHOFF		CLKx_PHOFF

/* PLL Reset
 * Resets the PLLA, PLLB when writing an 1 to the corresponding bit
 * Leave the reserved bits as default.
 * Note: 0x00001100 is my reset value for Si5351A 10-MSOP device
 */
#define SI5351_PLL_RESET		177u	/* R/W */
#define SI5351_PLLB_RST	(1u<<7)	/*!< PLLB_Reset, writing a 1 to this bit will reset PLLB. This is a self clearing bit */
#define SI5351_PLLA_RST	(1u<<5)	/*!< PLLA_Reset, writing a 1 to this bit will reset PLLA. This is a self clearing bit */
#define SI5351_PLL_RESET_RESERVED (0x5F)	/*!< leave as default, not specified */
#define SI5351_PLL_RESET_VALUE	(0xAC)	/*!< according to SI5351 datasheet Figure 10, page 21, applying PLLA, PLLB soft reset */

/* Crystal Internal Load Capacitance
 * Two bits determine the internal load capacitance value for the crystal. See the Crystal
 * Inputs section in the Si5351 data sheet
 * Default: SI5351_XTAL_CL_10_PF (10 pF load capacitors)
 */
#define SI5351_CRYSTAL_INTERNAL_LOAD_CAPACITANCE	183u	/* R/W */
#define SI5351_XTAL_CL_6_PF		(1u<<6)	/*!< Internal CL = 6 pF */
#define SI5351_XTAL_CL_8_PF		(2u<<6)	/*!< Internal CL = 8 pF */
#define SI5351_XTAL_CL_10_PF	(3u<<6)	/*!< Internal CL = 10 pF */
#define SI5351_XTAL_CL_MASK		(3u<<6)	/*!< Mask of the load capacitance */
#define SI5351_XTAL_RESERVED	(0x13)	/*!< RESERVED bit[5:0] should be written! (0b010010) */
/* There is some mystery about the value of these bits [5:0], in AN619 version 0.6, there are two values
 * miscellaneous PLL parameters PLLA_CL and PLLB_CL which should be set each of them to 2,
 * that could possibly be bits [5:4] and [2:1] ?
 * Reg183 contains suspicious bits which are rather unexplained on page 60, where there is stated that reg183, bits [5:0] should
 * be set to 010010b. Maybe it sets speed of the PLL loop?
 * After a bit of experimentation, it seems to be like this: Bit [0]: does nothing; Bits [2:1]: Setting one of these bits causes
 * the PLLA to become unstable.
 * Setting both of them also causes the SysInit and PLLB to be stuck in failure for a long time, then they start. It seems that
 * these bits allow you to tune the PLL to <200 MHz. Bit [3]: does nothing; Bits [5:4]: The same as [2:1], but for PLLB.
 */

/* Fanout Enable, set these bits to 1 for each fanout
 * note: the reset value of this SI5351 register is 0x00 */

#define SI5351_FANOUT_ENABLE	187u	/* R/W */
#define SI5351_CLKIN_FANOUT_EN	(1u<<7)	/*!< Enable fanout of CLKIN to clock output multiplexers. Set it to 1 */
#define SI5351_XO_FANOUT_EN	(1u<<6) 	/*!< Enable fanout of XO to clock output multiplexers. Set it to 1 */
#define SI5351_MS_FANOUT_EN	(1u<<4)		/*!< Enable fanout of Multisynth0 & Multisynth4 to all output multiplexers. Set it to 1 */
