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UPD HAL Driver V1.13.5.0

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This commit is contained in:
Thomas Kuschel 2024-10-15 22:04:13 +02:00
parent ec1e9c0622
commit 1084b4eff0
57 changed files with 72826 additions and 71839 deletions
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504
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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@ -37,14 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5) #if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #endif /* STM32H7 || STM32MP1 */
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@ -110,6 +108,10 @@ extern "C" {
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */ #endif /* STM32U5 */
#if defined(STM32H5)
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
#endif /* STM32H5 */
/** /**
* @} * @}
*/ */
@ -137,7 +139,8 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0) #if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif #endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx) #if defined(STM32F373xC) || defined(STM32F378xx)
@ -211,6 +214,11 @@ extern "C" {
#endif #endif
#endif #endif
#if defined(STM32U5)
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
#endif
/** /**
* @} * @}
*/ */
@ -231,9 +239,13 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases /** @defgroup CRC_Aliases CRC API aliases
* @{ * @{
*/ */
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #if defined(STM32H5) || defined(STM32C0)
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ #else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
#endif
/** /**
* @} * @}
*/ */
@ -275,7 +287,13 @@ extern "C" {
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif #endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #if defined(STM32H5)
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif #endif
@ -340,7 +358,8 @@ extern "C" {
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif #endif
@ -500,7 +519,7 @@ extern "C" {
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0) #if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else #else
@ -525,7 +544,20 @@ extern "C" {
#define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET #define OB_nBOOT0_SET OB_NBOOT0_SET
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */ #endif /* STM32U5 */
#if defined(STM32U0)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_USER_nBOOT1 OB_USER_NBOOT1
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U0 */
/** /**
* @} * @}
@ -569,6 +601,106 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */ #endif /* STM32G4 */
#if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
#define SYSCFG_ETH_MII SBS_ETH_MII
#define SYSCFG_ETH_RMII SBS_ETH_RMII
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SYSCFG_SAU SBS_SAU
#define SYSCFG_MPU_SEC SBS_MPU_SEC
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#else
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
#endif /* __ARM_FEATURE_CMSE */
#define SYSCFG_CLK SBS_CLK
#define SYSCFG_CLASSB SBS_CLASSB
#define SYSCFG_FPU SBS_FPU
#define SYSCFG_ALL SBS_ALL
#define SYSCFG_SEC SBS_SEC
#define SYSCFG_NSEC SBS_NSEC
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
#define HAL_SYSCFG_Lock HAL_SBS_Lock
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
#endif /* __ARM_FEATURE_CMSE */
#endif /* STM32H5 */
/** /**
* @} * @}
*/ */
@ -636,14 +768,16 @@ extern "C" {
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
STM32H757xx */
#endif /* STM32H7 */ #endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@ -665,13 +799,28 @@ extern "C" {
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5) #if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */ #endif /* STM32U5 || STM32H5 */
#if defined(STM32U5) #if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */ #endif /* STM32U5 */
#if defined(STM32WBA)
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
#endif /* STM32WBA */
/** /**
* @} * @}
*/ */
@ -681,7 +830,25 @@ extern "C" {
*/ */
#if defined(STM32U5) #if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */ #endif /* STM32U5 */
#if defined(STM32H5)
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
#endif /* STM32H5 */
#if defined(STM32H5) || defined(STM32U5)
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
#endif /* STM32H5 || STM32U5 */
/** /**
* @} * @}
*/ */
@ -862,7 +1029,8 @@ extern "C" {
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -1000,7 +1168,7 @@ extern "C" {
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif #endif
@ -1096,15 +1264,42 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
#endif /* STM32F7 */
#if defined(STM32H7) #if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
#endif /* STM32H7 */ #endif /* STM32F7 || STM32H7 || STM32L0 */
/** /**
* @} * @}
@ -1271,7 +1466,7 @@ extern "C" {
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif #endif
#if defined(STM32U5) || defined(STM32MP2) #if defined(STM32U5)
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
#endif #endif
@ -1388,26 +1583,36 @@ extern "C" {
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ the MAC transmitter) */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1) #if defined(STM32F1)
#else #else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */
#endif #endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@ -1415,6 +1620,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
/** /**
* @} * @}
*/ */
@ -1578,7 +1785,8 @@ extern "C" {
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0) #if defined(STM32L0)
@ -1587,8 +1795,10 @@ extern "C" {
#endif #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@ -1622,16 +1832,21 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@ -1756,6 +1971,17 @@ extern "C" {
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
@ -1764,6 +1990,8 @@ extern "C" {
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
@ -1774,10 +2002,25 @@ extern "C" {
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif #endif
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA || STM32H7RS */
/** /**
* @} * @}
*/ */
@ -1807,7 +2050,8 @@ extern "C" {
#define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@ -2064,7 +2308,8 @@ extern "C" {
#define COMP_STOP __HAL_COMP_DISABLE #define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK #define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@ -2089,8 +2334,8 @@ extern "C" {
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif #endif
# if defined(STM32F302xE) || defined(STM32F302xC) #if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@ -2123,8 +2368,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif #endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@ -2181,8 +2426,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif #endif
# if defined(STM32F373xC) ||defined(STM32F378xx) #if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@ -2199,7 +2444,7 @@ extern "C" {
__HAL_COMP_COMP2_EXTI_GET_FLAG()) __HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif #endif
#else #else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@ -2236,8 +2481,10 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
/** /**
* @} * @}
*/ */
@ -2396,7 +2643,9 @@ extern "C" {
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@ -2405,8 +2654,12 @@ extern "C" {
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
} while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
} while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@ -2442,8 +2695,8 @@ extern "C" {
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@ -2493,6 +2746,12 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#if defined(STM32C0)
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@ -2947,6 +3206,11 @@ extern "C" {
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif #endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@ -3411,7 +3675,12 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #if defined(STM32U0)
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
#endif
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3513,8 +3782,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@ -3550,7 +3821,97 @@ extern "C" {
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
#endif #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
#if defined(STM32H5)
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
#endif /* STM32H5 */
/** /**
* @} * @}
@ -3568,7 +3929,9 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@ -3603,6 +3966,13 @@ extern "C" {
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */ #endif /* STM32F1 */
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
defined (STM32H7) || \
defined (STM32L0) || defined (STM32L1) || \
defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
#define IS_ALARM IS_RTC_ALARM #define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER IS_RTC_TAMPER
@ -3621,6 +3991,11 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
#if defined (STM32H5)
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
#endif /* STM32H5 */
/** /**
* @} * @}
*/ */
@ -3632,7 +4007,7 @@ extern "C" {
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@ -3879,6 +4254,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/** /**
* @} * @}
*/ */
@ -3969,6 +4347,16 @@ extern "C" {
* @} * @}
*/ */
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32F7)
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
#endif /* STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
View File

@ -296,6 +296,8 @@ void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void); void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
View File

@ -54,7 +54,9 @@ typedef enum
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU

24
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
View File

@ -21,7 +21,7 @@
#define STM32L4xx_HAL_DMA_H #define STM32L4xx_HAL_DMA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -82,7 +82,7 @@ typedef enum
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef; } HAL_DMA_StateTypeDef;
/** /**
* @brief HAL DMA Error Code structure definition * @brief HAL DMA Error Code structure definition
@ -91,7 +91,7 @@ typedef enum
{ {
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef; } HAL_DMA_LevelCompleteTypeDef;
/** /**
@ -104,7 +104,7 @@ typedef enum
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef; } HAL_DMA_CallbackIDTypeDef;
/** /**
* @brief DMA handle Structure definition * @brief DMA handle Structure definition
@ -121,13 +121,13 @@ typedef struct __DMA_HandleTypeDef
void *Parent; /*!< Parent object state */ void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */ __IO uint32_t ErrorCode; /*!< DMA Error code */
@ -150,7 +150,7 @@ typedef struct __DMA_HandleTypeDef
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
}DMA_HandleTypeDef; } DMA_HandleTypeDef;
/** /**
* @} * @}
*/ */
@ -753,7 +753,7 @@ typedef struct __DMA_HandleTypeDef
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
@ -762,13 +762,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/** /**

10
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h
View File

@ -69,7 +69,7 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxSyncConfigTypeDef; } HAL_DMA_MuxSyncConfigTypeDef;
/** /**
@ -86,7 +86,7 @@ typedef struct
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxRequestGeneratorConfigTypeDef; } HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/** /**
* @} * @}
@ -211,10 +211,10 @@ typedef struct
*/ */
/* ------------------------- REQUEST -----------------------------------------*/ /* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/ /* ------------------------- SYNCHRO -----------------------------------------*/

1
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
View File

@ -783,6 +783,7 @@
/** /**
* @brief AF 14 selection * @brief AF 14 selection
*/ */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ #define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ #define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ #define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */

13
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
View File

@ -118,8 +118,6 @@ typedef enum
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */ process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef; } HAL_I2C_StateTypeDef;
@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */ HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
* @{ * @{
*/ */
/* Peripheral State, Mode and Error functions *********************************/ /* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/** /**
* @} * @}
@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \ (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
(~I2C_CR2_RD_WRN))) (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
View File

@ -4441,7 +4441,7 @@ typedef struct
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source

19
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h
View File

@ -640,6 +640,17 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
(__HANDLE__)->Instance->WPR = 0xFFU; \ (__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0u) } while(0u)
/**
* @brief Check whether if the RTC Calendar is initialized.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
#else
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
/** /**
* @brief Add 1 hour (summer time change). * @brief Add 1 hour (summer time change).
* @note This interface is deprecated. * @note This interface is deprecated.
@ -982,9 +993,15 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
RTC_DR_DU) RTC_DR_DU)
#define RTC_INIT_MASK 0xFFFFFFFFu #define RTC_INIT_MASK 0xFFFFFFFFu
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#if defined(STM32L412xx) || defined(STM32L422xx)
#define RTC_ICSR_RESERVED_MASK 0x000100FCu
#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#elif defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define RTC_ICSR_RESERVED_MASK 0x00011FFCu
#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#else #else
#define RTC_ISR_RESERVED_MASK 0x0003FFFFu
#define RTC_RSF_MASK (~(RTC_ISR_INIT | RTC_ISR_RSF)) #define RTC_RSF_MASK (~(RTC_ISR_INIT | RTC_ISR_RSF))
#endif #endif

6
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h
View File

@ -1616,7 +1616,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != 0U)) #define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & 0xFFB6FFFBU) == 0x00U) && ((INTERRUPT) != 0U))
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
@ -1647,7 +1647,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ #define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
(((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
#else #else
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != 0U)) #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != 0U))
#endif #endif
@ -1711,7 +1711,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg
((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \
((BDCU) == RTC_BINARY_MIX_BCDU_7)) ((BDCU) == RTC_BINARY_MIX_BCDU_7))
#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \ #define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \
(((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE)))
#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \ #define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \

24
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
View File

@ -416,7 +416,6 @@ typedef enum
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
@ -1001,8 +1000,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ #define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
/** /**
* @} * @}
*/ */
@ -1818,6 +1817,10 @@ mode.
((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8)) ((__PRESCALER__) == TIM_ICPSC_DIV8))
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
((__CHANNEL__) != (TIM_CHANNEL_6)))
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE)) ((__MODE__) == TIM_OPMODE_REPETITIVE))
@ -1838,8 +1841,9 @@ mode.
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2)) ((__CHANNEL__) == TIM_CHANNEL_2))
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \
@ -1892,7 +1896,6 @@ mode.
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE)) ((__STATE__) == TIM_BREAK_DISABLE))
@ -1951,8 +1954,8 @@ mode.
((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
@ -2232,7 +2235,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @{ * @{
*/ */
/* Timer Encoder functions ****************************************************/ /* Timer Encoder functions ****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
@ -2281,7 +2284,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength); uint32_t BurstLength, uint32_t DataLength);

134
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
View File

@ -86,103 +86,103 @@ typedef struct
/** @defgroup TIMEx_Remap TIM Extended Remapping /** @defgroup TIMEx_Remap TIM Extended Remapping
* @{ * @{
*/ */
#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /*!< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /*!< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
#if defined (ADC3) #if defined (ADC3)
#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */ #define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /*!< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */ #define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /*!< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /*!< TIM1_ETR is connected to ADC3 AWD3 */
#endif /* ADC3 */ #endif /* ADC3 */
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */ #define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 TI1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ #define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /*!< TIM1 TI1 is connected to COMP1 */
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
#if defined(COMP2) #if defined(COMP2)
#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */
#endif /* COMP2 */ #endif /* COMP2 */
#if defined (USB_OTG_FS) #if defined (USB_OTG_FS)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /*!< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */ #define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /*!< TIM2_ITR1 is connected to OTG_FS SOF */
#else #else
#if defined(STM32L471xx) #if defined(STM32L471xx)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /*!< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */ #define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /*!< No internal trigger on TIM2_ITR1 */
#else #else
#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ #define TIM_TIM2_ITR1_NONE 0x00000000U /*!< No internal trigger on TIM2_ITR1 */
#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ #define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /*!< TIM2_ITR1 is connected to USB SOF */
#endif /* STM32L471xx */ #endif /* STM32L471xx */
#endif /* USB_OTG_FS */ #endif /* USB_OTG_FS */
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ #define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */
#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ #define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /*!< TIM2_ETR is connected to LSE */
#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ #define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
#if defined(COMP2) #if defined(COMP2)
#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ #define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */
#endif /* COMP2 */ #endif /* COMP2 */
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ #define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2 TI4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ #define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /*!< TIM2 TI4 is connected to COMP1 output */
#if defined(COMP2) #if defined(COMP2)
#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ #define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /*!< TIM2 TI4 is connected to COMP2 output */
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /*!< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#endif /* COMP2 */ #endif /* COMP2 */
#if defined (TIM3) #if defined (TIM3)
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ #define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3 TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */ #define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /*!< TIM3 TI1 is connected to COMP1 output */
#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */ #define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /*!< TIM3 TI1 is connected to COMP2 output */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /*!< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ #define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ #define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */
#endif /* TIM3 */ #endif /* TIM3 */
#if defined (TIM8) #if defined (TIM8)
#if defined(ADC2) && defined(ADC3) #if defined(ADC2) && defined(ADC3)
#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /*!< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */ #define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /*!< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */ #define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /*!< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /*!< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /*!< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /*!< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /*!< TIM8_ETR is connected to ADC3 AWD3 */
#endif /* ADC2 && ADC3 */ #endif /* ADC2 && ADC3 */
#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */ #define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8 TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */ #define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /*!< TIM8 TI1 is connected to COMP1 */
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ #define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */ #define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */
#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */ #define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */
#endif /* TIM8 */ #endif /* TIM8 */
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */ #define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15 TI1 is connected to GPIO */
#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */ #define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /*!< TIM15 TI1 is connected to LSE */
#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */ #define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /*!< No redirection */
#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#if defined (TIM3) #if defined (TIM3)
#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM3 */ #endif /* TIM3 */
#if defined (TIM4) #if defined (TIM4)
#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM4 */ #endif /* TIM4 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */ #define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /*!< TIM16 TI1 is connected to LSI */
#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */ #define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /*!< TIM16 TI1 is connected to LSE */
#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /*!< TIM16 TI1 is connected to RTC wakeup interrupt */
#if defined (TIM16_OR1_TI1_RMP_2) #if defined (TIM16_OR1_TI1_RMP_2)
#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */ #define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /*!< TIM16 TI1 is connected to MSI */
#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /*!< TIM16 TI1 is connected to HSE div 32 */
#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /*!< TIM16 TI1 is connected to MCO */
#endif /* TIM16_OR1_TI1_RMP_2 */ #endif /* TIM16_OR1_TI1_RMP_2 */
#if defined (TIM17) #if defined (TIM17)
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ #define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */ #define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /*!< TIM17 TI1 is connected to MSI */
#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /*!< TIM17 TI1 is connected to HSE div 32 */
#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /*!< TIM17 TI1 is connected to MCO */
#endif /* TIM17 */ #endif /* TIM17 */
/** /**
* @} * @}
@ -200,11 +200,11 @@ typedef struct
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{ * @{
*/ */
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
#if defined (DFSDM1_Channel0) #if defined (DFSDM1_Channel0)
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#endif /* DFSDM1_Channel0 */ #endif /* DFSDM1_Channel0 */
/** /**
* @} * @}

32
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
View File

@ -198,7 +198,7 @@ typedef enum
/** /**
* @brief HAL UART Reception type definition * @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing. * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
* It is expected to admit following values : * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U, * HAL_UART_RECEPTION_TORTO = 0x02U,
@ -206,6 +206,17 @@ typedef enum
*/ */
typedef uint32_t HAL_UART_RxTypeTypeDef; typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
* @brief HAL UART Rx Event type definition
* @note HAL UART Rx Event type value aims to identify which type of Event has occurred
* leading to call of the RxEvent callback.
* This parameter can be a value of @ref UART_RxEvent_Type_Values :
* HAL_UART_RXEVENT_TC = 0x00U,
* HAL_UART_RXEVENT_HT = 0x01U,
* HAL_UART_RXEVENT_IDLE = 0x02U,
*/
typedef uint32_t HAL_UART_RxEventTypeTypeDef;
/** /**
* @brief UART handle Structure definition * @brief UART handle Structure definition
*/ */
@ -242,6 +253,8 @@ typedef struct __UART_HandleTypeDef
#endif /*USART_CR1_FIFOEN */ #endif /*USART_CR1_FIFOEN */
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
__IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@ -835,7 +848,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)
* @} * @}
*/ */
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values /** @defgroup UART_Reception_Type_Values UART Reception type values
* @{ * @{
*/ */
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@ -846,6 +859,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)
* @} * @}
*/ */
/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
* @{
*/
#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -1240,7 +1263,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)
* @{ * @{
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
/** @brief Get UART clok division factor from clock prescaler value. /** @brief Get UART clock division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ UART prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value.
* @retval UART clock division factor * @retval UART clock division factor
*/ */
@ -1255,8 +1278,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U)
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register with LPUART. /** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock. * @param __PCLK__ LPUART clock.

9
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
View File

@ -189,6 +189,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/** /**
* @} * @}
@ -208,10 +210,13 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
* @param __CLOCKSOURCE__ output variable. * @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__. * @retval UART clocking source, written in __CLOCKSOURCE__.
*/ */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) \
|| defined (STM32L485xx) || defined (STM32L486xx) \
|| defined (STM32L496xx) || defined (STM32L4A6xx) \ || defined (STM32L496xx) || defined (STM32L4A6xx) \
|| defined (STM32L4P5xx) || defined (STM32L4Q5xx) \ || defined (STM32L4P5xx) || defined (STM32L4Q5xx) \
|| defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) \
|| defined (STM32L4R9xx) || defined (STM32L4S5xx) \
|| defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
if((__HANDLE__)->Instance == USART1) \ if((__HANDLE__)->Instance == USART1) \

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
View File

@ -586,7 +586,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa
/* Set base address */ /* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */ /* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
} }
/** /**

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
View File

@ -454,7 +454,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
*/ */
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
{ {
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
MODIFY_REG(CRS->CFGR, MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);

6
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
View File

@ -70,7 +70,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] =
#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
/* Defines used for the bit position in the register and perform offsets */ /* Defines used for the bit position in the register and perform offsets */
#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U)) #define DMA_POSITION_CSELR_CXS(Channel) POSITION_VAL(DMA_CSELR_C1S << (((Channel)*4U) & 0x1FU))
/** /**
* @} * @}
*/ */
@ -1512,7 +1512,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
{ {
MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); DMA_CSELR_C1S << (((Channel) * 4U) & 0x1FU), PeriphRequest << DMA_POSITION_CSELR_CXS(Channel));
} }
/** /**
@ -1546,7 +1546,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{ {
return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS); DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS(Channel));
} }
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */

12
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h
View File

@ -968,7 +968,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
} }
/** /**
@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
} }
/** /**
@ -1207,7 +1207,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
} }
/** /**
@ -1606,7 +1606,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
@ -1902,7 +1902,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
} }
/** /**
@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
(void)(DMAMUXx); (void)(DMAMUXx);
return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
} }
/** /**

129
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h
View File

@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
} }
@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF * @retval Value between Min_Data=0x0 and Max_Data=0xF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
} }
@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
} }
@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
} }
@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
} }
@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register * @retval Address of data register
*/ */
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
{ {
uint32_t data_reg_addr; uint32_t data_reg_addr;
@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
} }
@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
} }
@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
} }
@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
} }
@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
} }
@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
} }
@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
} }
@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF * @retval Value between Min_Data=0x0 and Max_Data=0xF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
} }
@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF * @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
} }
@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF * @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
} }
@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF * @retval Value between Min_Data=0x0 and Max_Data=0xF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
} }
@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF * @retval Value between Min_Data=0x0 and Max_Data=0xF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
} }
@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
} }
@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
} }
@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
} }
@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF * @retval Value between Min_Data=0 and Max_Data=0xFFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
} }
@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
} }
@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF * @retval Value between Min_Data=0 and Max_Data=0xFFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
} }
@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{ {
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL); (ClockTimeout)) ? 1UL : 0UL);
@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
} }
@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
} }
@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
} }
@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
} }
@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
} }
@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
} }
@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
} }
@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
} }
@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
} }
@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
} }
@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
} }
@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
} }
@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
} }
@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
} }
@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
} }
@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
} }
@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
} }
@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
} }
@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
} }
@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
} }
@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
} }
@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
} }
@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
} }
@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
} }
@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF * @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
} }
@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
} }
@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
* @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ * @arg @ref LL_I2C_REQUEST_READ
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
} }
@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F * @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
} }
@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request) uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{ {
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); tmp);
} }
/** /**
@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
* @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ * @arg @ref LL_I2C_DIRECTION_READ
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
} }
@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F * @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
} }
@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
{ {
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
} }
@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF * @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
{ {
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
} }
@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance. * @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF * @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/ */
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
{ {
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
} }
@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
* @{ * @{
*/ */
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);

47
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h
View File

@ -502,7 +502,8 @@ typedef struct
((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
* LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#else #else
#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\ #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)\
(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) \
& LPUART_BRR_MASK) & LPUART_BRR_MASK)
#endif /* USART_PRESC_PRESCALER */ #endif /* USART_PRESC_PRESCALER */
@ -1492,7 +1493,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri
* @retval Baud Rate * @retval Baud Rate
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
uint32_t PrescalerValue)
#else #else
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk) __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk)
#endif /* USART_PRESC_PRESCALER */ #endif /* USART_PRESC_PRESCALER */
@ -1740,8 +1742,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUART
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
/** /**
* @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
@ -1778,8 +1779,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
/** /**
* @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
@ -2068,8 +2068,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
/** /**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
@ -2107,8 +2106,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
/** /**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt * @brief Enable TX Empty and TX FIFO Not Full Interrupt
@ -2253,8 +2251,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
/** /**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
@ -2292,8 +2289,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
/** /**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt * @brief Disable TX Empty and TX FIFO Not Full Interrupt
@ -2438,8 +2434,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
/** /**
* @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
@ -2477,8 +2472,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
/** /**
* @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
@ -2843,6 +2837,23 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
} }
#if defined(USART_CR1_FIFOEN)
/**
* @brief Request a Transmit data FIFO flush
* @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
* also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
}
#endif /* USART_CR1_FIFOEN */
/** /**
* @} * @}
*/ */

32
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
View File

@ -435,21 +435,21 @@ typedef struct
/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
* @{ * @{
*/ */
#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
#if defined(RCC_CCIPR_I2C2SEL) #if defined(RCC_CCIPR_I2C2SEL)
#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
#endif /* RCC_CCIPR_I2C2SEL */ #endif /* RCC_CCIPR_I2C2SEL */
#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
#if defined(RCC_CCIPR2_I2C4SEL) #if defined(RCC_CCIPR2_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
#endif /* RCC_CCIPR2_I2C4SEL */ #endif /* RCC_CCIPR2_I2C4SEL */
/** /**
* @} * @}
@ -705,13 +705,13 @@ typedef struct
/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
* @{ * @{
*/ */
#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ #define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
#if defined(RCC_CCIPR_I2C2SEL) #if defined(RCC_CCIPR_I2C2SEL)
#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ #define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
#endif /* RCC_CCIPR_I2C2SEL */ #endif /* RCC_CCIPR_I2C2SEL */
#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ #define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
#if defined(RCC_CCIPR2_I2C4SEL) #if defined(RCC_CCIPR2_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ #define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
#endif /* RCC_CCIPR2_I2C4SEL */ #endif /* RCC_CCIPR2_I2C4SEL */
/** /**
* @} * @}

20
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h
View File

@ -1524,7 +1524,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
/** /**
* @brief Get time format (AM or PM notation) * @brief Get time format (AM or PM notation)
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
/** /**
* @brief Get Hours in BCD format * @brief Get Hours in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
/** /**
* @brief Get Minutes in BCD format * @brief Get Minutes in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@ -1628,7 +1628,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
/** /**
* @brief Get Seconds in BCD format * @brief Get Seconds in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@ -1678,7 +1678,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
/** /**
* @brief Get time (hour, minute and second) in BCD format * @brief Get time (hour, minute and second) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@ -1825,7 +1825,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
/** /**
* @brief Get Year in BCD format * @brief Get Year in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n
@ -1859,7 +1859,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
/** /**
* @brief Get Week day * @brief Get Week day
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance * @param RTCx RTC Instance
@ -1906,7 +1906,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
/** /**
* @brief Get Month in BCD format * @brief Get Month in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n
@ -1948,7 +1948,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
/** /**
* @brief Get Day in BCD format * @brief Get Day in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n
@ -2010,7 +2010,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
/** /**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format * @brief Get date (WeekDay, Day, Month and Year) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit * before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter. * and __LL_RTC_GET_DAY are available to get independently each parameter.

38
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
View File

@ -60,6 +60,8 @@ extern "C" {
* @{ * @{
*/ */
#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */
/** /**
* @brief Power-down in Run mode Flash key * @brief Power-down in Run mode Flash key
*/ */
@ -154,22 +156,22 @@ extern "C" {
/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
* @{ * @{
*/ */
#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
/** /**
* @} * @}
*/ */
@ -772,7 +774,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
*/ */
__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
{ {
MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << POSITION_VAL((Line >> LL_EXTI_REGISTER_PINPOS_SHFT)));
} }
/** /**
@ -813,7 +815,7 @@ __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
*/ */
__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
{ {
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
} }
/** /**

34
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
View File

@ -31,7 +31,7 @@ extern "C" {
* @{ * @{
*/ */
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) #if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
/** @defgroup USART_LL USART /** @defgroup USART_LL USART
* @{ * @{
@ -65,6 +65,12 @@ static const uint32_t USART_PRESCALER_TAB[] =
#endif /* USART_PRESC_PRESCALER */ #endif /* USART_PRESC_PRESCALER */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Constants USART Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER) #if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros /** @defgroup USART_LL_Private_Macros USART Private Macros
@ -1660,7 +1666,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/ */
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
{ {
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
} }
@ -3116,8 +3122,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
/** /**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
@ -3157,8 +3162,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
/** /**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
@ -3643,8 +3647,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
/** /**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
@ -3684,8 +3687,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
/** /**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt * @brief Enable TX Empty and TX FIFO Not Full Interrupt
@ -3897,8 +3899,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
/** /**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
@ -3938,8 +3939,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
/** /**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt * @brief Disable TX Empty and TX FIFO Not Full Interrupt
@ -4153,8 +4153,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
/** /**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
@ -4194,8 +4193,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ #define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
/** /**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
View File

@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick * @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service. * configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks * @param Ticks Frequency of Ticks (Hz)
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)

5
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
View File

@ -53,7 +53,7 @@
*/ */
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */ #define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ #define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
@ -381,7 +381,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/** /**
* @brief Return tick frequency. * @brief Return tick frequency.
* @retval tick period in Hz * @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/ */
HAL_TickFreqTypeDef HAL_GetTickFreq(void) HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{ {

50
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
View File

@ -451,6 +451,37 @@ void HAL_MPU_Disable(void)
MPU->CTRL = 0; MPU->CTRL = 0;
} }
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/** /**
* @brief Initialize and configure the Region and the memory to be protected. * @brief Initialize and configure the Region and the memory to be protected.
@ -463,13 +494,6 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
@ -478,7 +502,13 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress; MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
@ -489,12 +519,6 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
} }
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */

78
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
View File

@ -156,7 +156,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
uint32_t tmp; uint32_t tmp;
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if(hdma == NULL) if (hdma == NULL)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/ */
DMA_CalcDMAMUXChannelBaseAndMask(hdma); DMA_CalcDMAMUXChannelBaseAndMask(hdma);
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{ {
/* if memory to memory force the request to 0*/ /* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM; hdma->Init.Request = DMA_REQUEST_MEM2MEM;
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{ {
/* Initialize parameters for DMAMUX request generator : /* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -249,7 +249,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
#if !defined (DMAMUX1) #if !defined (DMAMUX1)
/* Set request selection */ /* Set request selection */
if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
{ {
/* Write to DMA channel selection register */ /* Write to DMA channel selection register */
if (DMA1 == hdma->DmaBaseAddress) if (DMA1 == hdma->DmaBaseAddress)
@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA1 Channelx */ /* Configure request selection for DMA1 Channelx */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
} }
else /* DMA2 */ else /* DMA2 */
{ {
@ -266,7 +266,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA2 Channelx */ /* Configure request selection for DMA2 Channelx */
DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
} }
} }
@ -296,7 +296,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{ {
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if (NULL == hdma ) if (NULL == hdma)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -358,7 +358,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Reset Request generator parameters if any */ /* Reset Request generator parameters if any */
if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{ {
/* Initialize parameters for DMAMUX request generator : /* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State)
{ {
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
@ -481,7 +481,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State)
{ {
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Enable the transfer complete interrupt */ /* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */ /* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback ) if (NULL != hdma->XferHalfCpltCallback)
{ {
/* Enable the Half transfer complete interrupt as well */ /* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
@ -509,13 +509,13 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
#ifdef DMAMUX1 #ifdef DMAMUX1
/* Check if DMAMUX Synchronization is enabled*/ /* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{ {
/* Enable DMAMUX sync overrun IT*/ /* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
} }
if(hdma->DMAmuxRequestGen != 0U) if (hdma->DMAmuxRequestGen != 0U)
{ {
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/ /* enable the request gen overrun IT*/
@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral state */ /* Check the DMA peripheral state */
if(hdma->State != HAL_DMA_STATE_BUSY) if (hdma->State != HAL_DMA_STATE_BUSY)
{ {
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U) if (hdma->DMAmuxRequestGen != 0U)
{ {
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/ /* disable the request gen overrun IT*/
@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State) if (HAL_DMA_STATE_BUSY != hdma->State)
{ {
/* no transfer ongoing */ /* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U) if (hdma->DMAmuxRequestGen != 0U)
{ {
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/ /* disable the request gen overrun IT*/
@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
/* Call User Abort callback */ /* Call User Abort callback */
if(hdma->XferAbortCallback != NULL) if (hdma->XferAbortCallback != NULL)
{ {
hdma->XferAbortCallback(hdma); hdma->XferAbortCallback(hdma);
} }
@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
uint32_t temp; uint32_t temp;
uint32_t tickstart; uint32_t tickstart;
if(HAL_DMA_STATE_BUSY != hdma->State) if (HAL_DMA_STATE_BUSY != hdma->State)
{ {
/* no transfer ongoing */ /* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
@ -708,9 +708,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Get tick */ /* Get tick */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
while((hdma->DmaBaseAddress->ISR & temp) == 0U) while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
{ {
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
{ {
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
hdma->ErrorCode = HAL_DMA_ERROR_TE; hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */ /* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@ -729,9 +729,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
return HAL_ERROR; return HAL_ERROR;
} }
/* Check for the Timeout */ /* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY) if (Timeout != HAL_MAX_DELAY)
{ {
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{ {
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@ -749,10 +749,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
#if defined(DMAMUX1) #if defined(DMAMUX1)
/*Check for DMAMUX Request generator (if used) overrun status */ /*Check for DMAMUX Request generator (if used) overrun status */
if(hdma->DMAmuxRequestGen != 0U) if (hdma->DMAmuxRequestGen != 0U)
{ {
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */ /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{ {
/* Disable the request gen overrun interrupt */ /* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
@ -766,7 +766,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
} }
/* Check for DMAMUX Synchronization overrun */ /* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{ {
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
@ -776,10 +776,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
} }
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
if(HAL_DMA_FULL_TRANSFER == CompleteLevel) if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{ {
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU)); hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
/* Process unlocked */ /* Process unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@ -812,7 +812,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
{ {
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the half transfer interrupt */ /* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
@ -823,7 +823,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* DMA peripheral state is not updated in Half Transfer */ /* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */ /* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL) if (hdma->XferHalfCpltCallback != NULL)
{ {
/* Half transfer callback */ /* Half transfer callback */
hdma->XferHalfCpltCallback(hdma); hdma->XferHalfCpltCallback(hdma);
@ -833,7 +833,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Transfer Complete Interrupt management ***********************************/ /* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
{ {
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
/* Disable the transfer complete and error interrupt */ /* Disable the transfer complete and error interrupt */
@ -849,7 +849,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL) if (hdma->XferCpltCallback != NULL)
{ {
/* Transfer complete callback */ /* Transfer complete callback */
hdma->XferCpltCallback(hdma); hdma->XferCpltCallback(hdma);
@ -895,18 +895,18 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifier * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter. * a DMA_HandleTypeDef structure as parameter.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State)
{ {
switch (CallbackID) switch (CallbackID)
{ {
@ -957,7 +957,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State)
{ {
switch (CallbackID) switch (CallbackID)
{ {
@ -1072,7 +1072,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U) if (hdma->DMAmuxRequestGen != 0U)
{ {
/* Clear the DMAMUX request generator overrun flag */ /* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
@ -1086,7 +1086,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->CNDTR = DataLength; hdma->Instance->CNDTR = DataLength;
/* Memory to Peripheral */ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{ {
/* Configure DMA Channel destination address */ /* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress; hdma->Instance->CPAR = DstAddress;

30
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
View File

@ -114,14 +114,14 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */ /*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY) if (hdma->State == HAL_DMA_STATE_READY)
{ {
/* Process Locked */ /* Process Locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \ MODIFY_REG(hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \ (~DMAMUX_CxCR_DMAREQ_ID), \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
@ -147,7 +147,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy
* *
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -160,14 +160,14 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
/* check if the DMA state is ready /* check if the DMA state is ready
and DMA is using a DMAMUX request generator block and DMA is using a DMAMUX request generator block
*/ */
if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{ {
/* Process Locked */ /* Process Locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
/* Set the request generator new parameters */ /* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
pRequestGeneratorConfig->Polarity; pRequestGeneratorConfig->Polarity;
/* Process UnLocked */ /* Process UnLocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
* the configuration information for the specified DMA channel. * the configuration information for the specified DMA channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready /* check if the DMA state is ready
and DMA is using a DMAMUX request generator block and DMA is using a DMAMUX request generator block
*/ */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{ {
/* Enable the request generator*/ /* Enable the request generator*/
@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA channel. * the configuration information for the specified DMA channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@ -222,7 +222,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
/* check if the DMA state is ready /* check if the DMA state is ready
and DMA is using a DMAMUX request generator block and DMA is using a DMAMUX request generator block
*/ */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{ {
/* Disable the request generator*/ /* Disable the request generator*/
@ -245,7 +245,7 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{ {
/* Check for DMAMUX Synchronization overrun */ /* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{ {
/* Disable the synchro overrun interrupt */ /* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
@ -256,17 +256,17 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */ /* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL) if (hdma->XferErrorCallback != NULL)
{ {
/* Transfer error callback */ /* Transfer error callback */
hdma->XferErrorCallback(hdma); hdma->XferErrorCallback(hdma);
} }
} }
if(hdma->DMAmuxRequestGen != 0) if (hdma->DMAmuxRequestGen != 0)
{ {
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{ {
/* Disable the request gen overrun interrupt */ /* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
@ -277,7 +277,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
/* Update error code */ /* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL) if (hdma->XferErrorCallback != NULL)
{ {
/* Transfer error callback */ /* Transfer error callback */
hdma->XferErrorCallback(hdma); hdma->XferErrorCallback(hdma);

14
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
View File

@ -64,7 +64,7 @@
(++) Provide exiting handle as parameter. (++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter. (++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@ -75,7 +75,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending(). (#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending(). (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@ -346,7 +346,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
assert_param(IS_EXTI_GPIO_PIN(linepos)); assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u]; regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
} }
} }
@ -537,7 +537,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
uint32_t linepos; uint32_t linepos;
uint32_t maskline; uint32_t maskline;
uint32_t offset; uint32_t offset;
(void)Edge;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));
@ -572,7 +574,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
__IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t maskline; uint32_t maskline;
uint32_t offset; uint32_t offset;
(void)Edge;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));

8
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
View File

@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
* @brief De-initialize the GPIOx peripheral registers to their default reset values. * @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written. * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None * @retval None
*/ */
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* @brief Read the specified input port pin. * @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read. * @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value. * @retval The input port pin value.
*/ */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* *
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written. * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit. * @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values: * This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_RESET: to clear the port pin
@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* until the next reset. * until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked. * @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None * @retval None
*/ */
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)

662
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

8
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
View File

@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void)
========================================= =========================================
[..] [..]
(+) Entry: (+) Entry:
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void)
=============================== ===============================
[..] [..]
(+) Entry: (+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2. (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void)
and Standby circuitry. and Standby circuitry.
(++) Entry: (++) Entry:
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@ -264,7 +264,7 @@ void HAL_PWR_DisableBkUpAccess(void)
SRAM and registers contents are lost except for backup domain registers. SRAM and registers contents are lost except for backup domain registers.
(+) Entry: (+) Entry:
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit: (+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,

4
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
View File

@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
/** /**
* @brief Enable battery charging. * @brief Enable battery charging.
* When VDD is present, charge the external battery on VBAT thru an internal resistor. * When VDD is present, charge the external battery on VBAT through an internal resistor.
* @param ResistorSelection specifies the resistor impedance. * @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
/* Configure EXTI 35 to 38 interrupts if so required: /* Configure EXTI 35 to 38 interrupts if so required:
scan thru PVMType to detect which PVMx is set and scan through PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */ configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType) switch (sConfigPVM->PVMType)
{ {

8
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
View File

@ -398,6 +398,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off * supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass. * first and then HSE On or HSE Bypass.
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@ -1318,7 +1320,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
@ -1852,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
/* MSI 8Mhz */ /* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */ latency = FLASH_LATENCY_1; /* 1WS */
} }
else
{
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
/* nothing to do */
}
} }
#endif #endif
} }

6
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
View File

@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret; status = ret;
} }
} }
else
{
/* nothing to do */
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2)
(+++) Default values can be set for frequency Error Measurement (reload and error limit) (+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming. and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and sychronization frequencies values directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which (##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values. (+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration (+++) Configures CRS registers with synchronization configuration

28
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c
View File

@ -319,6 +319,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Set RTC state */ /* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY; hrtc->State = HAL_RTC_STATE_BUSY;
/* Check whether the calendar needs to be initialized */
if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
/* Disable the write protection for RTC registers */ /* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@ -345,6 +348,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Configure the Binary mode */ /* Configure the Binary mode */
MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
#endif #endif
}
/* Exit Initialization mode */ /* Exit Initialization mode */
status = RTC_ExitInitMode(hrtc); status = RTC_ExitInitMode(hrtc);
@ -358,12 +362,20 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
#endif #endif
}
/* Enable the write protection for RTC registers */ /* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
} }
else
{
/* The calendar is already initialized */
status = HAL_OK;
}
if (status == HAL_OK)
{
hrtc->State = HAL_RTC_STATE_READY;
} }
} }
@ -2492,11 +2504,15 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{ {
uint32_t tickstart; uint32_t tickstart;
/* Clear RSF flag */ #if defined(STM32L412xx) || defined(STM32L422xx)
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK));
#elif defined (STM32L4P5xx) || defined (STM32L4Q5xx)
/* Clear RSF flag (use a read-modify-write sequence to preserve the other read-write bits) */
hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
#else #else
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
#endif #endif
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -2666,7 +2682,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value)
while (temp >= 10U) while (temp >= 10U)
{ {
bcdhigh++; bcdhigh++;
temp -= 10; temp -= 10U;
} }
return ((uint8_t)(bcdhigh << 4U) | temp); return ((uint8_t)(bcdhigh << 4U) | temp);

2
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
View File

@ -1930,7 +1930,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Clear the bits that are going to be configured and leave the others unchanged */ /* Clear the bits that are going to be configured and leave the others unchanged */
tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
{ {
tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
} }

148
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
View File

@ -888,7 +888,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */ /* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@ -980,7 +980,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel) switch (Channel)
{ {
@ -1059,7 +1059,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */ /* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@ -1221,7 +1221,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel) switch (Channel)
{ {
@ -1557,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */ /* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@ -1649,7 +1649,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel) switch (Channel)
{ {
@ -1728,7 +1728,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */ /* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@ -1889,7 +1889,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel) switch (Channel)
{ {
@ -2133,7 +2133,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */ /* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@ -2181,7 +2181,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Disable the Input Capture channel */ /* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */ /* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@ -2305,7 +2305,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel) switch (Channel)
{ {
@ -2381,7 +2381,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Set the TIM channel state */ /* Set the TIM channel state */
@ -2536,7 +2536,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Disable the Input Capture channel */ /* Disable the Input Capture channel */
@ -3027,7 +3027,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @param sConfig TIM Encoder Interface configuration structure * @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
{ {
uint32_t tmpsmcr; uint32_t tmpsmcr;
uint32_t tmpccmr1; uint32_t tmpccmr1;
@ -3833,13 +3833,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/ */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{ {
uint32_t itsource = htim->Instance->DIER;
uint32_t itflag = htim->Instance->SR;
/* Capture compare 1 event */ /* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{ {
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */ /* Input capture event */
@ -3867,11 +3870,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* Capture compare 2 event */ /* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */ /* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@ -3897,11 +3900,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* Capture compare 3 event */ /* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */ /* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@ -3927,11 +3930,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* Capture compare 4 event */ /* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */ /* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@ -3957,11 +3960,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* TIM Update event */ /* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim); htim->PeriodElapsedCallback(htim);
#else #else
@ -3970,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* TIM Break input event */ /* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim); htim->BreakCallback(htim);
#else #else
@ -3983,9 +3987,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* TIM Break2 input event */ /* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{ {
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@ -3996,11 +4000,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* TIM Trigger detection event */ /* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim); htim->TriggerCallback(htim);
#else #else
@ -4009,11 +4013,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
} }
} }
/* TIM commutation event */ /* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{ {
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{ {
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim); htim->CommutationCallback(htim);
#else #else
@ -4564,7 +4568,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength)
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
@ -5987,8 +5992,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
{ {
return HAL_ERROR; return HAL_ERROR;
} }
/* Process locked */
__HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY) if (htim->State == HAL_TIM_STATE_READY)
{ {
@ -6184,9 +6187,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */
__HAL_UNLOCK(htim);
return status; return status;
} }
@ -6230,9 +6230,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY) if (htim->State == HAL_TIM_STATE_READY)
{ {
switch (CallbackID) switch (CallbackID)
@ -6469,9 +6466,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */
__HAL_UNLOCK(htim);
return status; return status;
} }
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@ -6978,6 +6972,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler /* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */ and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG; TIMx->EGR = TIM_EGR_UG;
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
}
} }
/** /**
@ -6992,11 +6993,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 1: Reset the CC1E Bit */ /* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E; TIMx->CCER &= ~TIM_CCER_CC1E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
@ -7067,11 +7069,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 2: Reset the CC2E Bit */ /* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E; TIMx->CCER &= ~TIM_CCER_CC2E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
@ -7100,7 +7103,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U); tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */ /* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE; tmpccer &= ~TIM_CCER_CC2NE;
} }
if (IS_TIM_BREAK_INSTANCE(TIMx)) if (IS_TIM_BREAK_INSTANCE(TIMx))
@ -7143,11 +7145,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 3: Reset the CC2E Bit */ /* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E; TIMx->CCER &= ~TIM_CCER_CC3E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
@ -7217,11 +7220,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 4: Reset the CC4E Bit */ /* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E; TIMx->CCER &= ~TIM_CCER_CC4E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
@ -7278,11 +7282,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the output: Reset the CCxE Bit */ /* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E; TIMx->CCER &= ~TIM_CCER_CC5E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */ /* Get the TIMx CCMR1 register value */
@ -7331,11 +7336,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer; uint32_t tmpccer;
uint32_t tmpcr2; uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the output: Reset the CCxE Bit */ /* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E; TIMx->CCER &= ~TIM_CCER_CC6E;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */ /* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2; tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */ /* Get the TIMx CCMR1 register value */
@ -7519,9 +7525,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
uint32_t tmpccer; uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */ /* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E; TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1; tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Select the Input */ /* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@ -7609,9 +7615,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer; uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */ /* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E; TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1; tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Select the Input */ /* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 &= ~TIM_CCMR1_CC2S;
@ -7648,9 +7654,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
uint32_t tmpccer; uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */ /* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E; TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1; tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
/* Set the filter */ /* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 &= ~TIM_CCMR1_IC2F;
@ -7692,9 +7698,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer; uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */ /* Disable the Channel 3: Reset the CC3E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E; TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2; tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
/* Select the Input */ /* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 &= ~TIM_CCMR2_CC3S;
@ -7740,9 +7746,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer; uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */ /* Disable the Channel 4: Reset the CC4E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E; TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2; tmpccmr2 = TIMx->CCMR2;
tmpccer = TIMx->CCER;
/* Select the Input */ /* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 &= ~TIM_CCMR2_CC4S;

37
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
View File

@ -837,7 +837,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */ /* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER; tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{ {
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
} }
@ -1083,17 +1083,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts. (+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers. (+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers.
(+) Start the Complementary Input Capture measurement.
(+) Stop the Complementary Input Capture.
(+) Start the Complementary Input Capture and enable interrupts.
(+) Stop the Complementary Input Capture and disable interrupts.
(+) Start the Complementary Input Capture and enable DMA transfers.
(+) Stop the Complementary Input Capture and disable DMA transfers.
(+) Start the Complementary One Pulse generation.
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
@endverbatim @endverbatim
* @{ * @{
*/ */
@ -1319,7 +1308,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */ /* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER; tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{ {
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
} }
@ -2105,7 +2094,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput, uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx; uint32_t tmporx;
@ -2547,7 +2535,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
*/ */
/** /**
* @brief Hall commutation changed callback in non-blocking mode * @brief Commutation callback in non-blocking mode
* @param htim TIM handle * @param htim TIM handle
* @retval None * @retval None
*/ */
@ -2561,7 +2549,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/ */
} }
/** /**
* @brief Hall commutation changed half complete callback in non-blocking mode * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle * @param htim TIM handle
* @retval None * @retval None
*/ */
@ -2576,7 +2564,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
} }
/** /**
* @brief Hall Break detection callback in non-blocking mode * @brief Break detection callback in non-blocking mode
* @param htim TIM handle * @param htim TIM handle
* @retval None * @retval None
*/ */
@ -2591,7 +2579,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
} }
/** /**
* @brief Hall Break2 detection callback in non blocking mode * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle * @param htim: TIM handle
* @retval None * @retval None
*/ */
@ -2742,15 +2730,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
} }
} }
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
}
}
else else
{ {
/* nothing to do */ /* nothing to do */
@ -2819,13 +2798,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
{ {
uint32_t tmp; uint32_t tmp;
tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */ /* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp; TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */ /* Set or reset the CCxNE Bit */
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
} }
/** /**
* @} * @}

325
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
View File

@ -109,7 +109,7 @@
[..] [..]
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. weak function.
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
This function allows to reset following callbacks: This function allows to reset following callbacks:
@ -135,10 +135,10 @@
[..] [..]
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions: all callbacks are set to the corresponding weak functions:
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_UART_Init() reset to the legacy weak functions in the HAL_UART_Init()
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand). keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@ -155,7 +155,7 @@
[..] [..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used. and weak callbacks are used.
@endverbatim @endverbatim
@ -211,8 +211,8 @@
/** @addtogroup UART_Private_Functions /** @addtogroup UART_Private_Functions
* @{ * @{
*/ */
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@ -368,17 +368,19 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */ /* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR) if (UART_SetConfig(huart) == HAL_ERROR)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In asynchronous mode, the following bits must be kept cleared: /* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
@ -433,17 +435,19 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */ /* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR) if (UART_SetConfig(huart) == HAL_ERROR)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In half-duplex mode, the following bits must be kept cleared: /* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/ - SCEN and IREN bits in the USART_CR3 register.*/
@ -519,17 +523,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */ /* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR) if (UART_SetConfig(huart) == HAL_ERROR)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In LIN mode, the following bits must be kept cleared: /* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/ - SCEN and IREN bits in the USART_CR3 register.*/
@ -603,17 +609,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */ /* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR) if (UART_SetConfig(huart) == HAL_ERROR)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* In multiprocessor mode, the following bits must be kept cleared: /* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
@ -676,6 +684,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_RESET; huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart); __HAL_UNLOCK(huart);
@ -715,7 +724,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/** /**
* @brief Register a User UART Callback * @brief Register a User UART Callback
* To be used instead of the weak predefined callback * To be used to override the weak predefined callback
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle * @param huart uart handle
* @param CallbackID ID of the callback to be registered * @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values: * This parameter can be one of the following values:
@ -749,8 +761,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY) if (huart->gState == HAL_UART_STATE_READY)
{ {
switch (CallbackID) switch (CallbackID)
@ -842,14 +852,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
status = HAL_ERROR; status = HAL_ERROR;
} }
__HAL_UNLOCK(huart);
return status; return status;
} }
/** /**
* @brief Unregister an UART Callback * @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback * UART callaback is redirected to the weak predefined callback
* @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle * @param huart uart handle
* @param CallbackID ID of the callback to be unregistered * @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values: * This parameter can be one of the following values:
@ -874,8 +885,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(huart);
if (HAL_UART_STATE_READY == huart->gState) if (HAL_UART_STATE_READY == huart->gState)
{ {
switch (CallbackID) switch (CallbackID)
@ -969,8 +978,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
status = HAL_ERROR; status = HAL_ERROR;
} }
__HAL_UNLOCK(huart);
return status; return status;
} }
@ -992,10 +999,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
return HAL_ERROR; return HAL_ERROR;
} }
/* Process locked */ if (huart->RxState == HAL_UART_STATE_READY)
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
{ {
huart->RxEventCallback = pCallback; huart->RxEventCallback = pCallback;
} }
@ -1006,9 +1010,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */
__HAL_UNLOCK(huart);
return status; return status;
} }
@ -1022,10 +1023,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ if (huart->RxState == HAL_UART_STATE_READY)
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_READY)
{ {
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
} }
@ -1036,8 +1034,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */
__HAL_UNLOCK(huart);
return status; return status;
} }
@ -1160,8 +1156,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE; huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX; huart->gState = HAL_UART_STATE_BUSY_TX;
@ -1183,12 +1177,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
pdata16bits = NULL; pdata16bits = NULL;
} }
__HAL_UNLOCK(huart);
while (huart->TxXferCount > 0U) while (huart->TxXferCount > 0U)
{ {
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{ {
huart->gState = HAL_UART_STATE_READY;
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
if (pdata8bits == NULL) if (pdata8bits == NULL)
@ -1206,6 +1201,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{ {
huart->gState = HAL_UART_STATE_READY;
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
@ -1250,8 +1247,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE; huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX; huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@ -1278,13 +1273,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
pdata16bits = NULL; pdata16bits = NULL;
} }
__HAL_UNLOCK(huart);
/* as long as data have to be received */ /* as long as data have to be received */
while (huart->RxXferCount > 0U) while (huart->RxXferCount > 0U)
{ {
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{ {
huart->RxState = HAL_UART_STATE_READY;
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
if (pdata8bits == NULL) if (pdata8bits == NULL)
@ -1331,8 +1326,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData; huart->pTxBuffPtr = pData;
huart->TxXferSize = Size; huart->TxXferSize = Size;
huart->TxXferCount = Size; huart->TxXferCount = Size;
@ -1355,8 +1348,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t
huart->TxISR = UART_TxISR_8BIT_FIFOEN; huart->TxISR = UART_TxISR_8BIT_FIFOEN;
} }
__HAL_UNLOCK(huart);
/* Enable the TX FIFO threshold interrupt */ /* Enable the TX FIFO threshold interrupt */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
} }
@ -1372,8 +1363,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t
huart->TxISR = UART_TxISR_8BIT; huart->TxISR = UART_TxISR_8BIT;
} }
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */ /* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
} }
@ -1388,8 +1377,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t
huart->TxISR = UART_TxISR_8BIT; huart->TxISR = UART_TxISR_8BIT;
} }
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */ /* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
#endif /* USART_CR1_FIFOEN */ #endif /* USART_CR1_FIFOEN */
@ -1422,8 +1409,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
/* Set Reception type to Standard reception */ /* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@ -1465,8 +1450,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
huart->pTxBuffPtr = pData; huart->pTxBuffPtr = pData;
huart->TxXferSize = Size; huart->TxXferSize = Size;
huart->TxXferCount = Size; huart->TxXferCount = Size;
@ -1494,8 +1477,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t
/* Set error code to DMA */ /* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA; huart->ErrorCode = HAL_UART_ERROR_DMA;
__HAL_UNLOCK(huart);
/* Restore huart->gState to ready */ /* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY; huart->gState = HAL_UART_STATE_READY;
@ -1505,8 +1486,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t
/* Clear the TC flag in the ICR register */ /* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
__HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit /* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */ in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@ -1541,8 +1520,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
/* Set Reception type to Standard reception */ /* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@ -1574,8 +1551,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState; const HAL_UART_StateTypeDef rxstate = huart->RxState;
__HAL_LOCK(huart);
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX)) (gstate == HAL_UART_STATE_BUSY_TX))
{ {
@ -1593,8 +1568,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
} }
__HAL_UNLOCK(huart);
return HAL_OK; return HAL_OK;
} }
@ -1605,8 +1578,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
*/ */
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{ {
__HAL_LOCK(huart);
if (huart->gState == HAL_UART_STATE_BUSY_TX) if (huart->gState == HAL_UART_STATE_BUSY_TX)
{ {
/* Enable the UART DMA Tx request */ /* Enable the UART DMA Tx request */
@ -1628,8 +1599,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
} }
__HAL_UNLOCK(huart);
return HAL_OK; return HAL_OK;
} }
@ -2547,6 +2516,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* Last bytes received, so no need as the abort is immediate */ /* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx); (void)HAL_DMA_Abort(huart->hdmarx);
} }
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/ /*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
@ -2555,6 +2529,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
} }
else
{
/* If DMA is in Circular mode, Idle event is to be reported to user
even if occurring after a Transfer Complete event from DMA */
if (nb_remaining_rx_data == huart->RxXferSize)
{
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
{
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
}
}
return; return;
} }
else else
@ -2588,6 +2584,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
huart->RxISR = NULL; huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/ /*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data); huart->RxEventCallback(huart, nb_rx_data);
@ -3403,6 +3404,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
/* Check whether the set of advanced features to configure is properly set */ /* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure TX pin active level inversion */ /* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{ {
@ -3424,13 +3432,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
} }
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure RX overrun detection disabling */ /* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{ {
@ -3488,6 +3489,17 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
/* Wait until TEACK flag is set */ /* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{ {
/* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
#endif /* USART_CR1_FIFOEN */
huart->gState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
/* Timeout occurred */ /* Timeout occurred */
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
@ -3499,6 +3511,19 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
/* Wait until REACK flag is set */ /* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{ {
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->RxState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
/* Timeout occurred */ /* Timeout occurred */
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
@ -3508,6 +3533,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY; huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart); __HAL_UNLOCK(huart);
@ -3535,43 +3561,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
{ {
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{ {
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
__HAL_UNLOCK(huart);
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{ {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
huart->ErrorCode = HAL_UART_ERROR_ORE;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_ERROR;
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{ {
/* Clear Receiver Timeout flag*/ /* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) /* Blocking error : transfer is aborted
interrupts for the interrupt process */ Set the UART state ready to be able to start again the process,
#if defined(USART_CR1_FIFOEN) Disable Rx Interrupts if ongoing */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | UART_EndRxTransfer(huart);
USART_CR1_TXEIE_TXFNFIE));
#else
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
#endif /* USART_CR1_FIFOEN */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO; huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */ /* Process Unlocked */
@ -3626,8 +3648,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
huart->RxISR = UART_RxISR_8BIT_FIFOEN; huart->RxISR = UART_RxISR_8BIT_FIFOEN;
} }
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE) if (huart->Init.Parity != UART_PARITY_NONE)
{ {
@ -3647,8 +3667,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
huart->RxISR = UART_RxISR_8BIT; huart->RxISR = UART_RxISR_8BIT;
} }
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE) if (huart->Init.Parity != UART_PARITY_NONE)
{ {
@ -3670,8 +3688,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
huart->RxISR = UART_RxISR_8BIT; huart->RxISR = UART_RxISR_8BIT;
} }
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE) if (huart->Init.Parity != UART_PARITY_NONE)
{ {
@ -3724,15 +3740,12 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
/* Set error code to DMA */ /* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA; huart->ErrorCode = HAL_UART_ERROR_DMA;
__HAL_UNLOCK(huart);
/* Restore huart->RxState to ready */ /* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR; return HAL_ERROR;
} }
} }
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */ /* Enable the UART Parity Error Interrupt */
if (huart->Init.Parity != UART_PARITY_NONE) if (huart->Init.Parity != UART_PARITY_NONE)
@ -3887,6 +3900,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
} }
} }
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */ If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -3921,6 +3938,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{ {
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Half Transfer */
huart->RxEventType = HAL_UART_RXEVENT_HT;
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */ If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -4399,6 +4420,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
/* Clear RxISR function pointer */ /* Clear RxISR function pointer */
huart->RxISR = NULL; huart->RxISR = NULL;
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : */ If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -4414,6 +4448,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
/* Clear IDLE Flag */ /* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
} }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/ /*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize); huart->RxEventCallback(huart, huart->RxXferSize);
@ -4482,6 +4517,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
/* Clear RxISR function pointer */ /* Clear RxISR function pointer */
huart->RxISR = NULL; huart->RxISR = NULL;
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : */ If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -4497,6 +4545,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
/* Clear IDLE Flag */ /* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
} }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/ /*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize); huart->RxEventCallback(huart, huart->RxXferSize);
@ -4613,6 +4662,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
/* Clear RxISR function pointer */ /* Clear RxISR function pointer */
huart->RxISR = NULL; huart->RxISR = NULL;
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : */ If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -4628,6 +4690,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
/* Clear IDLE Flag */ /* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
} }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/ /*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize); huart->RxEventCallback(huart, huart->RxXferSize);
@ -4647,6 +4710,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
HAL_UART_RxCpltCallback(huart); HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} }
break;
} }
} }
@ -4763,6 +4827,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
/* Clear RxISR function pointer */ /* Clear RxISR function pointer */
huart->RxISR = NULL; huart->RxISR = NULL;
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
/* Check current reception Mode : /* Check current reception Mode :
If Reception till IDLE event has been selected : */ If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@ -4778,6 +4855,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
/* Clear IDLE Flag */ /* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
} }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/ /*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize); huart->RxEventCallback(huart, huart->RxXferSize);
@ -4797,6 +4875,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
HAL_UART_RxCpltCallback(huart); HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} }
break;
} }
} }

64
stm32l4a6zg-f0x.at1/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
View File

@ -215,17 +215,19 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Set the UART Communication parameters */ /* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR) if (UART_SetConfig(huart) == HAL_ERROR)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DEM); SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
@ -627,7 +629,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
/* Disable UART */ /* Disable UART */
__HAL_UART_DISABLE(huart); __HAL_UART_DISABLE(huart);
/* Enable FIFO mode */ /* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_DISABLE; huart->FifoMode = UART_FIFOMODE_DISABLE;
@ -778,11 +780,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE; huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX; huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */ /* Init tickstart for timeout management */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -806,8 +807,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
pdata16bits = NULL; pdata16bits = NULL;
} }
__HAL_UNLOCK(huart);
/* Initialize output number of received elements */ /* Initialize output number of received elements */
*RxLen = 0U; *RxLen = 0U;
@ -824,6 +823,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
/* If Set, and data has already been received, this means Idle Event is valid : End reception */ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U) if (*RxLen > 0U)
{ {
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY;
return HAL_OK; return HAL_OK;
@ -889,7 +889,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
*/ */
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */ /* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY) if (huart->RxState == HAL_UART_STATE_READY)
@ -899,16 +899,12 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/ /* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size); (void)UART_Start_Receive_IT(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{ {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
@ -922,7 +918,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR; status = HAL_ERROR;
} }
}
return status; return status;
} }
@ -961,10 +956,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
return HAL_ERROR; return HAL_ERROR;
} }
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/ /* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size); status = UART_Start_Receive_DMA(huart, pData, Size);
@ -994,6 +988,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
} }
} }
/**
* @brief Provide Rx Event type that has lead to RxEvent callback execution.
* @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
* of reception process is provided to application through calls of Rx Event callback (either default one
* HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
* Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
* to Rx Event callback execution.
* @note This function is expected to be called within the user implementation of Rx Event Callback,
* in order to provide the accurate value :
* In Interrupt Mode :
* - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
* - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
* received data is lower than expected one)
* In DMA Mode :
* - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
* - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
* - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
* received data is lower than expected one).
* In DMA mode, RxEvent callback could be called several times;
* When DMA is configured in Normal Mode, HT event does not stop Reception process;
* When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
* @param huart UART handle.
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
*/
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
return (huart->RxEventType);
}
/** /**
* @} * @}
*/ */