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ADD si5351_read_register_debug for reading the value of a bulk of register

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This commit is contained in:
Tom Kuschel
2022-05-17 12:59:33 +02:00
parent f4a61ee06f
commit 83c3043d2c
4 changed files with 101 additions and 20 deletions
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14
Core/Inc/stm32_si5351.h
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@ -108,12 +108,26 @@ typedef enum {
#ifndef SI5351_NUMBER_OF_OUTPUTS
#define SI5351_NUMBER_OF_OUTPUTS 8
#endif
#ifdef __arm__
#ifdef __ARM_BIG_ENDIAN
#define for_endian(size) for (int i = 0; i < size; ++i)
#define last_loop_endian (i==size-1)
#else
#define for_endian(size) for (int i = size - 1; i >= 0; --i)
#define last_loop_endian (i==0)
#endif
#else
#error "Endianness not detected or another compiler"
#endif
/* Exported functions --------------------------------------------------------*/
si5351_inst_t si5351_init(void * i2c_handle, uint32_t xtal_frequency, uint8_t i2c_address);
int si5351_deinit(si5351_inst_t si5351_handle);
int si5351_isready(si5351_inst_t inst);
int si5351_program(si5351_inst_t inst);
char * si5351_read_debug_msg(si5351_inst_t inst);
char * si5351_read_register_debug(si5351_inst_t inst, char *buf, size_t bufsize, uint8_t regaddr);
#ifdef __cplusplus
} /* extern "C" */

25
Core/Inc/stm32_si5351_reg.h
View File

@ -605,9 +605,6 @@ Synth1 divider. */
/* #define SI5351_MULTISYNTH1_PARAMETER_2_LO_RESET_VALUE 0xXX */
/* Multisynth2 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth2 Divider. */
@ -714,9 +711,6 @@ Synth2 divider. */
/* #define SI5351_MULTISYNTH2_PARAMETER_2_LO_RESET_VALUE 0xXX */
/* Multisynth3 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth3 Divider. */
@ -823,9 +817,6 @@ Synth3 divider. */
/* #define SI5351_MULTISYNTH3_PARAMETER_2_LO_RESET_VALUE 0xXX */
/* MULTISYNTH5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth4 Divider. */
@ -932,13 +923,6 @@ Synth3 divider. */
/* #define SI5351_MULTISYNTH4_PARAMETER_2_LO_RESET_VALUE 0xXX */
/* Multisynth5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth5 Divider. */
@ -1088,6 +1072,15 @@ even integers greater than or equal to 6. All other divide values are invalid. *
#define R6_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R6_DIV (7u<<4)
/* PLL Reset
* Resets the PLLA, PLLB when writing an 1 to the corresponding bit
* Leave the reserved bits as default.
* Note: 0x00001100 is my reset value for Si5351A 10-MSOP device
*/
#define SI5351_PLL_RESET 177u /* R/W */
#define SI5351_PLLB_RST (1u<<7) /*!< PLLB_Reset, writing a 1 to this bit will reset PLLB. This is a self clearing bit */
#define SI5351_PLLA_RST (1u<<5) /*!< PLLA_Reset, writing a 1 to this bit will reset PLLA. This is a self clearing bit */
#define SI5351_PLL_RESET_RESERVED (0x5F) /*!< leave as default, not specified */
/* Crystal Internal Load Capacitance
* Two bits determine the internal load capacitance value for the crystal. See the Crystal