thesis/f0x.at1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

First Commit, build a driver for the Si5153

Browse Source
This commit is contained in:
Tom Kuschel 2022-05-15 22:42:00 +02:00
commit 8f5cdc1f54
139 changed files with 167839 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

190
.cproject Normal file
View File

@ -0,0 +1,190 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1733161466" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.2063761826" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L4A6ZGTx" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1635473366" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.534674924" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.826437132" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1358635365" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1488063577" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-L4A6ZG" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1669066834" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || NUCLEO-L4A6ZG || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy || || || USE_HAL_DRIVER | STM32L4A6xx || || Drivers | Core/Startup | Middlewares | Core || || || ${workspace_loc:/${ProjName}/STM32L4A6ZGTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.246809598" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/stm32l4a6zg-blinky}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.250331425" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.170688257" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.561012640" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.2118173975" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEBUG"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1466960261" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1022456538" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.610940627" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.649572492" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2142020706" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEBUG"/>
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32L4A6xx"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1609223839" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.650651857" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.747400999" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.91015543" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1870504915" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2080247656" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1708312028" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L4A6ZGTX_FLASH.ld}" valueType="string"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1741193466" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.870430631" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1381543434" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1291684609" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.831677900" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1406338177" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.837179267" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1674512652" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1633984742" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.907883227" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1478081658" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1815301460" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L4A6ZGTx" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.877690103" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1532358815" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.567161963" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.186331672" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1676473540" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-L4A6ZG" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.123670443" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || NUCLEO-L4A6ZG || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/CMSIS/Device/ST/STM32L4xx/Include | ../Drivers/STM32L4xx_HAL_Driver/Inc | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy || || || USE_HAL_DRIVER | STM32L4A6xx || || Drivers | Core/Startup | Middlewares | Core || || || ${workspace_loc:/${ProjName}/STM32L4A6ZGTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1482029968" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/stm32l4a6zg-blinky}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.741935225" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.35377680" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.742521961" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.54368074" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.399703450" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.160121054" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.677078772" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.377649046" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
<listOptionValue builtIn="false" value="STM32L4A6xx"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.2054422072" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="../Core/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc"/>
<listOptionValue builtIn="false" value="../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L4xx/Include"/>
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
</option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.105765051" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1355958959" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.2119650028" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1540697389" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1985302522" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.672487053" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L4A6ZGTX_FLASH.ld}" valueType="string"/>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1318224735" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1500052630" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.102548191" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1095781071" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1832646924" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1978431512" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1893396908" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1825797237" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1400330101" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.897862584" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="stm32l4a6zg-blinky.null.2144122152" name="stm32l4a6zg-blinky"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.2081800086.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.399703450;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.105765051">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2117444367.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1022456538;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.650651857">
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/stm32l4a6zg-freertos"/>
</configuration>
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/stm32l4a6zg-freertos"/>
</configuration>
</storageModule>
</cproject>

5
.gitignore vendored Normal file
View File

@ -0,0 +1,5 @@
# Do not track:
.mxproject
.settings/
Debug/
Release/

32
.project Normal file
View File

@ -0,0 +1,32 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>stm32l4a6zg-freertos</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

173
Core/Inc/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,173 @@
/* USER CODE BEGIN Header */
/*
* FreeRTOS Kernel V10.3.1
* Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* USER CODE END Header */
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* These parameters and more are described within the 'configuration' section of the
* FreeRTOS API documentation available on the FreeRTOS.org web site.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* Section where include file can be added */
/* USER CODE END Includes */
/* Ensure definitions are only used by the compiler, and not by the assembler. */
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#ifndef CMSIS_device_header
#define CMSIS_device_header "stm32l4xx.h"
#endif /* CMSIS_device_header */
#define configENABLE_FPU 0
#define configENABLE_MPU 0
#define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 56 )
#define configMINIMAL_STACK_SIZE ((uint16_t)128)
#define configTOTAL_HEAP_SIZE ((size_t)3000)
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed
if lengths will always be less than the number of bytes in a size_t. */
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH 256
/* The following flag must be enabled only when using newlib */
#define configUSE_NEWLIB_REENTRANT 1
/* CMSIS-RTOS V2 flags */
#define configUSE_OS2_THREAD_SUSPEND_RESUME 1
#define configUSE_OS2_THREAD_ENUMERATE 1
#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1
#define configUSE_OS2_THREAD_FLAGS 1
#define configUSE_OS2_TIMER 1
#define configUSE_OS2_MUTEX 1
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xQueueGetMutexHolder 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_eTaskGetState 1
/*
* The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
* by the application thus the correct define need to be enabled below
*/
#define USE_FreeRTOS_HEAP_4
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
/* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
/* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */
#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
/* USER CODE BEGIN Defines */
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
/* USER CODE END Defines */
#endif /* FREERTOS_CONFIG_H */

47
Core/Inc/at1_defines.h Normal file
View File

@ -0,0 +1,47 @@
/******************************************************************************
* File Name : at1_defines.h
* Description : constants and defines for the project f0x.at1
******************************************************************************
* @author: Thomas Kuschel KW4NZ
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef AT1_DEFINES_H
#define AT1_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Private includes ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#ifndef STR_HELPER
#define STR_HELPER(x) #x
#define STR(x) STR_HELPER(x)
#endif
#define VERSION_MAJOR 0
#define VERSION_MINOR 1
#define PROGRAM_ID "f0x.at1 Version " STR(VERSION_MAJOR) "." STR(VERSION_MINOR)
#define VERSION_STRING STR(VERSION_MAJOR) "." STR(VERION_MINOR)
//#define DATE __DATE__
#define AUTHOR_STRING "Tom Kuschel KW4NZ"
// From SI5351 datasheet:
#define SI5351_I2C_ADDR (0x60 << 1)
/* Exported variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* AT1_DEFINES_H */

100
Core/Inc/main.h Normal file
View File

@ -0,0 +1,100 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define B1_Pin GPIO_PIN_13
#define B1_GPIO_Port GPIOC
#define LD3_Pin GPIO_PIN_14
#define LD3_GPIO_Port GPIOB
#define USB_OverCurrent_Pin GPIO_PIN_5
#define USB_OverCurrent_GPIO_Port GPIOG
#define USB_PowerSwitchOn_Pin GPIO_PIN_6
#define USB_PowerSwitchOn_GPIO_Port GPIOG
#define STLK_RX_Pin GPIO_PIN_7
#define STLK_RX_GPIO_Port GPIOG
#define STLK_TX_Pin GPIO_PIN_8
#define STLK_TX_GPIO_Port GPIOG
#define LD1_Pin GPIO_PIN_7
#define LD1_GPIO_Port GPIOC
#define USB_SOF_Pin GPIO_PIN_8
#define USB_SOF_GPIO_Port GPIOA
#define USB_VBUS_Pin GPIO_PIN_9
#define USB_VBUS_GPIO_Port GPIOA
#define USB_ID_Pin GPIO_PIN_10
#define USB_ID_GPIO_Port GPIOA
#define USB_DM_Pin GPIO_PIN_11
#define USB_DM_GPIO_Port GPIOA
#define USB_DP_Pin GPIO_PIN_12
#define USB_DP_GPIO_Port GPIOA
#define TMS_Pin GPIO_PIN_13
#define TMS_GPIO_Port GPIOA
#define TCK_Pin GPIO_PIN_14
#define TCK_GPIO_Port GPIOA
#define SWO_Pin GPIO_PIN_3
#define SWO_GPIO_Port GPIOB
#define LD2_Pin GPIO_PIN_7
#define LD2_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

525
Core/Inc/si5351.h Normal file
View File

@ -0,0 +1,525 @@
/*
* si5351.h
*
* Created on: Feb 16, 2018
* Author: Petr Polasek
*
* To make this library useable on any other device than
* STM32Fxxx Cortex Mx, please edit these parts of the library:
*
* DEFINES:
* SI5351_I2C_PERIPHERAL - the I2C peripheral name according
* to your devices HAL library
* I2C_TIMEOUT - time for the communication to time out
*
* TYPEDEFS:
* Si5351_ConfigTypeDef - the I2Cx parameter should be changed
* so that its type corresponds to your HAL library
*
* FUNCTIONS:
* Si5351_WriteRegister
* Si5351_ReadRegister
* You need to write your own I2C handlers here
*
*/
#ifndef SI5351_H_
#define SI5351_H_
#include "stm32l4xx_hal.h"
#define SI5351_I2C_ADDRESS 0xC0 //default I2C address of Si5351
#define SI5351_I2C_PERIPHERAL I2C1 //default I2C interface
#define SI5351_XTAL_FREQ 25000000 // sets default value, 25000000 for 25 MHz, 27000000 for 27 MHz
#define SI5351_CLKIN_FREQ 0 // set in Hz
#ifdef I2C_TIMEOUT
#undef I2C_TIMEOUT
#endif
#define I2C_TIMEOUT 100000 //I2C timeout for wait loops
#define SI5351_TIMEOUT (I2C_TIMEOUT * 10)
#ifndef ENABLESTATE
#define ENABLESTATE
typedef enum
{
OFF = 0,
ON = 1
} EnableState;
#endif
/*
* This section contains register addresses and bit masks for
* the device status registers.
*/
#define REG_DEV_STATUS 0
#define DEV_SYS_INIT_MASK 0x80
#define DEV_LOL_B_MASK 0x40
#define DEV_LOL_A_MASK 0x20
#define DEV_LOS_CLKIN_MASK 0x10
#define DEV_LOS_XTAL_MASK 0x08
#define DEV_REVID_MASK 0x03
#define REG_DEV_STICKY 1
#define DEV_STKY_SYS_INIT_MASK 0x80
#define DEV_STKY_LOL_B_MASK 0x40
#define DEV_STKY_LOL_A_MASK 0x20
#define DEV_STKY_LOS_CLKIN_MASK 0x10
#define DEV_STKY_LOS_XTAL_MASK 0x08
#define REG_INT_MASK 2
#define INT_MASK_SYS_INIT_MASK 0x80
#define INT_MASK_LOL_B_MASK 0x40
#define INT_MASK_LOL_A_MASK 0x20
#define INT_MASK_LOS_CLKIN_MASK 0x10
#define INT_MASK_LOS_XTAL_MASK 0x08
/*
* This section contains data structures for configuring the
* oscillator, VCXO and CLKIN section.
*/
#define REG_XTAL_CL 183
#define XTAL_CL_MASK 0xC0
#define PLL_CL_MASK 0x36
//this sets the crystal load capacitance
typedef enum
{
XTAL_Load_4_pF = 0x00,
XTAL_Load_6_pF = 0x40,
XTAL_Load_8_pF = 0x80,
XTAL_Load_10_pF = 0xC0
} Si5351_XTALLoadTypeDef;
//The following is an unexplained parameter. However someone from SiLabs called it "VCO load cap".
//Lower settings seem to be more stable on higher frequencies, higher settings are more stable on lower frequencies allowing to tune the PLL to <200 MHz.
typedef enum
{
PLL_Capacitive_Load_0 = 0,
PLL_Capacitive_Load_1 = 1,
PLL_Capacitive_Load_2 = 2
} Si5351_PLLCapacitiveLoadTypeDef;
#define REG_CLKIN_DIV 15
#define CLKIN_MASK 0xC0
//this sets the CLKIN pre-divider, after division, CLKIN should
//fall between 10-40 MHz
typedef enum
{
CLKINDiv_Div1 = 0x00,
CLKINDiv_Div2 = 0x40,
CLKINDiv_Div4 = 0x80,
CLKINDiv_Div8 = 0xC0
} Si5351_CLKINDivTypeDef;
#define REG_FANOUT_EN 187
#define FANOUT_CLKIN_EN_MASK 0x80
#define FANOUT_XO_EN_MASK 0x40
#define FANOUT_MS_EN_MASK 0x10
#define REG_VCXO_PARAM_0_7 162
#define REG_VCXO_PARAM_8_15 163
#define REG_VCXO_PARAM_16_21 164
#define VCXO_PARAM_16_21_MASK 0x3F
#define VCXO_PARAM_MASK 0x003FFFFF
#define APR_MINIMUM 30 //minimum pull range
#define APR_MAXIMUM 240 //maximum pull range
#define CLKIN_MINIMUM 10000 //minimum CLKIN frequency after division in kHz
#define CLKIN_MAXIMUM 40000 //maximum CLKIN frequency after division in kHz
typedef struct
{
Si5351_XTALLoadTypeDef OSC_XTAL_Load; //capacitive load of XTAL, 10pF by default
Si5351_CLKINDivTypeDef CLKIN_Div; //CLKIN predivision, input f to PLL must be 10-40 MHz
uint8_t VCXO_Pull_Range_ppm; //can range from +-30 ppm to 240ppm
} Si5351_OSCConfigTypeDef;
/*
* This section contains data structures for configuring the
* PLL (PLLA and PLLB)
*/
#define REG_PLL_CLOCK_SOURCE 15
#define PLLA_CLOCK_SOURCE_MASK 0x04
#define PLLB_CLOCK_SOURCE_MASK 0x08
//this selects the clock source for the PLL
typedef enum
{
PLL_Clock_Source_XTAL = 0x00,
PLL_Clock_Source_CLKIN = 0x0C //0x04 for PLLA, 0x08 for PLLB, use mask!
} Si5351_PLLClockSourceTypeDef;
#define REG_FB_INT 22
#define FB_INT_MASK 0x40
#define REG_PLL_RESET 177
#define PLLA_RESET_MASK 0x20
#define PLLB_RESET_MASK 0x80
#define REG_MSN_P1_0_7 30
#define REG_MSN_P1_8_15 29
#define REG_MSN_P1_16_17 28
#define MSN_P1_16_17_MASK 0x03
#define REG_MSN_P2_0_7 33
#define REG_MSN_P2_8_15 32
#define REG_MSN_P2_16_19 31
#define MSN_P2_16_19_MASK 0x0F
#define REG_MSN_P3_0_7 27
#define REG_MSN_P3_8_15 26
#define REG_MSN_P3_16_19 31
#define MSN_P3_16_19_MASK 0xF0
#define MSNA_MSNB_OFFSET 8
typedef struct
{
uint32_t PLL_Multiplier_Integer;
uint32_t PLL_Multiplier_Numerator;
uint32_t PLL_Multiplier_Denominator;
Si5351_PLLClockSourceTypeDef PLL_Clock_Source;
Si5351_PLLCapacitiveLoadTypeDef PLL_Capacitive_Load;
} Si5351_PLLConfigTypeDef;
/*
* This section contains data structures for configuring the
* Spread Spectrum feature.
*/
#define REG_SSC_MODE 151
#define SSC_MODE_MASK 0x80
//this selects the Spread Spectrum mode
typedef enum
{
SS_Mode_DownSpread = 0x00,
SS_Mode_CenterSpread = 0x80
} Si5351_SSModeTypeDef;
typedef enum
{
SS_NCLK_0 = 0x00,
SS_NCLK_1 = 0x10,
SS_NCLK_2 = 0x20,
SS_NCLK_3 = 0x30,
SS_NCLK_4 = 0x40,
SS_NCLK_5 = 0x50,
SS_NCLK_6 = 0x60,
SS_NCLK_7 = 0x70,
SS_NCLK_8 = 0x80,
SS_NCLK_9 = 0x90,
SS_NCLK_10 = 0xA0,
SS_NCLK_11 = 0xB0,
SS_NCLK_12 = 0xC0,
SS_NCLK_13 = 0xD0,
SS_NCLK_14 = 0xE0,
SS_NCLK_15 = 0xF0
} Si5351_SSNCLKTypeDef;
#define REG_SSDN_P1_0_7 153
#define REG_SSDN_P1_8_11 154
#define SSDN_P1_8_11_MASK 0x0F
#define REG_SSDN_P2_0_7 150
#define REG_SSDN_P2_8_14 149
#define SSDN_P2_8_14_MASK 0x7F
#define REG_SSDN_P3_0_7 152
#define REG_SSDN_P3_8_14 151
#define SSDN_P3_8_14_MASK 0x7F
#define REG_SSUDP_0_7 155
#define REG_SSUDP_8_11 154
#define SSUDP_8_11_MASK 0xF0
#define REG_SSUP_P1_0_7 160
#define REG_SSUP_P1_8_11 161
#define SSUP_P1_8_11_MASK 0x0F
#define REG_SSUP_P2_0_7 157
#define REG_SSUP_P2_8_14 156
#define SSUP_P2_8_14_MASK 0x7F
#define REG_SSUP_P3_0_7 159
#define REG_SSUP_P3_8_14 158
#define SSUP_P3_8_14_MASK 0x7F
#define REG_SSC_EN 149
#define SSC_EN_MASK 0x80
#define REG_SS_NCLK 161
#define SS_NCLK_MASK 0xF0
typedef struct
{
uint32_t SS_Amplitude_ppm; //amplitude of the SS feature in ppm of center frequency
EnableState SS_Enable;
Si5351_SSModeTypeDef SS_Mode;
Si5351_SSNCLKTypeDef SS_NCLK;
} Si5351_SSConfigTypeDef;
/*
* This section contains data structures for configuring the
* Output Multisynth.
*/
//this selects the Multisynth clock source
typedef enum
{
MS_Clock_Source_PLLA = 0x00,
MS_Clock_Source_PLLB = 0x20
} Si5351_MSClockSourceTypeDef;
#define REG_MS_P1_0_7 46
#define REG_MS_P1_8_15 45
#define REG_MS_P1_16_17 44
#define MS_P1_16_17_MASK 0x03
#define REG_MS_P2_0_7 49
#define REG_MS_P2_8_15 48
#define REG_MS_P2_16_19 47
#define MS_P2_16_19_MASK 0x0F
#define REG_MS_P3_0_7 43
#define REG_MS_P3_8_15 42
#define REG_MS_P3_16_19 47
#define MS_P3_16_19_MASK 0xF0
#define REG_MS67_P1 90
#define REG_MS_INT 16
#define MS_INT_MASK 0x40
#define REG_MS_DIVBY4 44
#define MS_DIVBY4_MASK 0x0C
#define REG_MS_SRC 16
#define MS_SRC_MASK 0x20
#define MS_SETUP_STEP 1
#define MS_DIVIDER_STEP 8
typedef struct
{
Si5351_MSClockSourceTypeDef MS_Clock_Source; //select source on MS input
uint32_t MS_Divider_Integer; //the integer part of divider, called "a"
uint32_t MS_Divider_Numerator; //the numerator, called "b"
uint32_t MS_Divider_Denominator; //the denominator, called "c"
} Si5351_MSConfigTypeDef; //sets MS divider ( a+(b/c) ) and clock (PLLA/PLLB)
/*
* This section contains data structures for configuring the
* CLK, R divider and output stage (joined together because they make
* a tight block without any multiplexer).
*/
#define REG_CLK_SRC 16
#define CLK_SRC_MASK 0x0C
//this sets the CLK source clock
typedef enum
{
CLK_Clock_Source_XTAL = 0x00,
CLK_Clock_Source_CLKIN = 0x04,
CLK_Clock_Source_MS0_MS4 = 0x08, //this uses MS0 for CLK0..3 and MS4 for CLK4..7
CLK_Clock_Source_MS_Own = 0x0C //this uses MSx for CLKx
} Si5351_CLKClockSourceTypeDef; //configures multiplexer on CLK input
#define REG_CLK_R_DIV 44
#define CLK_R_DIV_MASK 0x70
#define REG_CLK_R67_DIV 92
#define CLK_R67_DIV_MASK 0x07
//this sets the R divider ratio
typedef enum
{
CLK_R_Div1 = 0x00,
CLK_R_Div2 = 0x10,
CLK_R_Div4 = 0x20,
CLK_R_Div8 = 0x30,
CLK_R_Div16 = 0x40,
CLK_R_Div32 = 0x50,
CLK_R_Div64 = 0x60,
CLK_R_Div128 = 0x70
} Si5351_CLKRDivTypeDef;
#define REG_CLK_DIS_STATE 24
#define CLK_DIS_STATE_MASK 0x03
//this sets output buffer behaviour when disabled
typedef enum
{
CLK_Disable_State_LOW = 0x00,
CLK_Disable_State_HIGH = 0x01,
CLK_Disable_State_HIGH_Z = 0x02, //three-stated when off
CLK_Disable_State_ALWAYS_ON = 0x03 //cannot be disabled
} Si5351_CLKDisableStateTypeDef;
#define REG_CLK_IDRV 16
#define CLK_IDRV_MASK 0x03
//this sets current drive of the output buffer
typedef enum
{
CLK_I_Drv_2mA = 0x00,
CLK_I_Drv_4mA = 0x01,
CLK_I_Drv_6mA = 0x02,
CLK_I_Drv_8mA = 0x03
} Si5351_CLKIDrvTypeDef;
#define REG_CLK_PHOFF 165
#define CLK_PHOFF_MASK 0x7F
#define REG_CLK_EN 3
#define REG_CLK_INV 16
#define CLK_INV_MASK 0x10
#define REG_CLK_PDN 16
#define CLK_PDN_MASK 0x80
#define REG_CLK_OEB 9
#define CLK_PHOFF_STEP 1
#define CLK_SETUP_STEP 1
#define CLK_R_DIV_STEP 8
typedef struct
{
Si5351_CLKClockSourceTypeDef CLK_Clock_Source; //clock source
/* this sets the time offset of the CLK channel, basic unit
* is one quarter of the VCO period (90deg offset),
* set it to 4*fVCO*toffset, the value is 7-bit, the max time offset
* varies between 35 and 53 ns (1 cycle for 28 and 19 MHz, respectively)
* according to the current frequency of the VCO
*/
uint8_t CLK_QuarterPeriod_Offset;
Si5351_CLKRDivTypeDef CLK_R_Div; //R divider value (only powers of 2)
EnableState CLK_Invert; //invert output clock
EnableState CLK_Enable; //enable flag
EnableState CLK_PowerDown; //powerdown flag
Si5351_CLKDisableStateTypeDef CLK_Disable_State; //sets output behaviour when disabled
Si5351_CLKIDrvTypeDef CLK_I_Drv; //output driver current drive strength
EnableState CLK_Use_OEB_Pin; //allows using OEB pin to enable clock
} Si5351_CLKConfigTypeDef;
/*
* This section contains main data structure for Si5351 configuration
*/
typedef struct
{
/*
* These are frequencies of the input clocks, set it in Hz.
*/
uint32_t f_XTAL;
uint32_t f_CLKIN;
//Interrupt masking - enabling it disables the int source from pulling INTR low
EnableState Interrupt_Mask_SysInit;
EnableState Interrupt_Mask_PLLB;
EnableState Interrupt_Mask_PLLA;
EnableState Interrupt_Mask_CLKIN;
EnableState Interrupt_Mask_XTAL;
//Fanout enable - enables internal clock routing
EnableState Fanout_MS_EN;
EnableState Fanout_XO_EN;
EnableState Fanout_CLKIN_EN;
I2C_TypeDef *I2Cx; //the I2C interface that will be used
uint8_t HW_I2C_Address; //I2C address of the Si5351 for the packages with A0 pin
//(also, some duds with strange address reported)
Si5351_OSCConfigTypeDef OSC; //Oscillator, CLKIN and VCXO settings
Si5351_PLLConfigTypeDef PLL[2]; //PLL settings for PLLA and PLLB
Si5351_MSConfigTypeDef MS[8]; //MultiSynth[0..7] settings
Si5351_CLKConfigTypeDef CLK[8]; //CLK[0..7], R divider and output stage settings
Si5351_SSConfigTypeDef SS; //spread spectrum settings
} Si5351_ConfigTypeDef;
/*
* Typedefs for selecting PLL, MS and CLK to be used
*/
//this selects PLL channel
typedef enum
{
PLL_A = 0,
PLL_B = 1
} Si5351_PLLChannelTypeDef;
//this selects Multisynth channel
typedef enum
{
MS0 = 0,
MS1 = 1,
MS2 = 2,
MS3 = 3,
MS4 = 4,
MS5 = 5,
MS6 = 6,
MS7 = 7
} Si5351_MSChannelTypeDef;
//this selects CLK channel
typedef enum
{
CLK0 = 0,
CLK1 = 1,
CLK2 = 2,
CLK3 = 3,
CLK4 = 4,
CLK5 = 5,
CLK6 = 6,
CLK7 = 7
} Si5351_CLKChannelTypeDef;
//this selects device status flag
typedef enum
{
StatusBit_SysInit = DEV_SYS_INIT_MASK,
StatusBit_PLLA = DEV_STKY_LOL_A_MASK,
StatusBit_PLLB = DEV_LOL_B_MASK,
StatusBit_CLKIN = DEV_LOS_CLKIN_MASK,
StatusBit_XTAL = DEV_LOS_XTAL_MASK,
} Si5351_StatusBitTypeDef;
//these write to and read from a Si5351 register, for porting
//purposes, these functions should be the only ones which should need edits
int Si5351_WriteRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address, uint8_t reg_data);
uint8_t Si5351_ReadRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address);
void Si5351_StructInit(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_OSCConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
EnableState Si5351_CheckStatusBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
EnableState Si5351_CheckStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
void Si5351_InterruptConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_ClearStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
void Si5351_PLLConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel);
void Si5351_PLLReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel);
void Si5351_PLLSimultaneousReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_SSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_MSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_MSChannelTypeDef MS_Channel);
void Si5351_CLKPowerCmd(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel);
void Si5351_CLKConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel);
int Si5351_Init(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
#endif /* SI5351_H_ */

624
Core/Inc/stm32_si5351.h Normal file
View File

@ -0,0 +1,624 @@
/******************************************************************************
* File Name : stm32_si5351.h
* Description : STM32 library/driver for the Si5351 clock chip
* from Skyworks Solutions, Inc. (former SiLabs)
******************************************************************************
* @author: Thomas Kuschel KW4NZ, created 2022-05-11
*
* originally written by Petr Polasek, created Feb 16, 2018
******************************************************************************
* DO NOT EDIT THIS FILE FOR CONFIGURATION, USE THE FOLLOWING PROCEDURE:
*
* Inside your main.c program or within your STM32 code:
* Include this header to the the main.c: #include "stm32_si5351.h"
* You've to initialize the I2C functionality first (e.g. with STM32CubeIDE)
* Afterwards, when there is a handle like "I2C_HandleTypeDef hi2c1;",
* you simply initialize this stm32_si5351 library in your main.c ,
* just after the MX_I2C1_Init();
* so between the USER CODE like using the given i2c handle "hi2c1":
*
* /\* USER CODE BEGIN 2 *\/
* si5351_init(&hi2c1);
* /\* USER CODE END 2 *\/
*
* The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed
* address plus a user selectable LSB bit as shown in Figure 6 of the datasheet.
* The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful
* for applications that require more than one Si5351 on a single I2C bus.
* Only the Si5351A 20-QFN and Si5351A 16-QFN have the A0 LSB pin option.
* If a part does not have the A0 pin, the default address is 0x60 with
* the A0 bit set to 0.
*
* So additionally you may drive more then one Si5351 at the same or
* another I2C bus when calling the init function with the given
* I2C bus address (default: 0x60)
* ( - internally this I2C address is shifted to the left
* for the proper usage of the I2C HAL driver i.e. it becomes 0xC0 )
*
* Example:
* \\ Define handlers for the sum of three SI5351 clock generators:
* si5351_HandleTypeDef h_si5351[3];
*
* // 1st SI5351 chip and with an A0 = 0:
* h_si5351[0] = si5351_init(&hi2c1, 25000000, 0x60);
* // 2nd SI5351 chip on the same I2C bus "hi2c1" but address line A0 = 1
* h_si5351[1] = si5351_init(&hi2c1, 27000000, 0x61);
* // 3rd SI5351 chip on another IC2 bus with handle "hi2c2" *\/
* h_si5351[2] = si5351_init(&hi2c2, 25000000, 0x60);
*
* PROs:
* The library is preemptive and can be used within an operating system.
* All structures and used variables are dynamically allocated.
* CONs:
* Not fully tested, but used with FreeRTOS and with 2 I2C bus systems.
*
* CHANGES:
* - Removed several defines, enums, etc. from the header file, b/c we do not
* want to export them to other programs
*
*
* The old simple example to get 50 kHz output with an 25 MHz crystal:
* Si5351_ConfigTypeDef Si5351_ConfigStruct;
* Si5351_StructInit(&Si5351_ConfigStruct); //initialize the structure with default "safe" values
* Si5351_ConfigStruct.OSC.OSC_XTAL_Load = XTAL_Load_8_pF; //use 8 pF load for crystal
* Si5351_ConfigStruct.PLL[0].PLL_Clock_Source = PLL_Clock_Source_XTAL; //select xrystal as clock input for the PLL
* Si5351_ConfigStruct.PLL[0].PLL_Multiplier_Integer = 32; //multiply the clock frequency by 32, this gets us 800 MHz clock
* Si5351_ConfigStruct.MS[0].MS_Clock_Source = MS_Clock_Source_PLLA; //select PLLA as clock source for MultiSynth 0
* Si5351_ConfigStruct.MS[0].MS_Divider_Integer = 250; //divide the 800 MHz by 250 this gets us 3.2 MHz
* Si5351_ConfigStruct.CLK[0].CLK_R_Div = CLK_R_Div64; //divide the MultiSynth output by 64, this gets us 50 kHz
* Si5351_ConfigStruct.CLK[0].CLK_Enable = ON; //turn on the output
* Si5351_Init(&Si5351_ConfigStruct); //apply the changes
*
******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32_SI5351_H
#define STM32_SI5351_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/* Private includes ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Si5351 instance typedef */
typedef struct __SI5351_HandleTypeDef *si5351_inst_t;
/* Exported constants --------------------------------------------------------*/
/** @enum errno_t Error Number Constants
*/
typedef enum {
EPERM = 1, /*!< Operation not permitted */
ENOMEM = 12, /*!< Out of memory */
ENODEV = 19, /*!< No such device */
EINVAL = 22, /*!< Invalid argument */
EADDRINUSE = 98 /*!< Address already in use */
} si5351_errno_t;
/* Exported variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
si5351_inst_t si5351_init(void * i2c_handle, uint32_t xtal_frequency, uint8_t i2c_address);
int si5351_deinit(si5351_inst_t si5351_handle);
int si5351_isready(si5351_inst_t inst);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* STM32_SI5351_H */
/*
* si5351.h
*
* Created on: Feb 16, 2018
* Author: Petr Polasek
*
* To make this library useable on any other device than
* STM32Fxxx Cortex Mx, please edit these parts of the library:
*
* DEFINES:
* SI5351_I2C_PERIPHERAL - the I2C peripheral name according
* to your devices HAL library
* I2C_TIMEOUT - time for the communication to time out
*
* TYPEDEFS:
* Si5351_ConfigTypeDef - the I2Cx parameter should be changed
* so that its type corresponds to your HAL library
*
* FUNCTIONS:
* Si5351_WriteRegister
* Si5351_ReadRegister
* You need to write your own I2C handlers here
*
*/
#if 0
#ifndef ENABLESTATE
#define ENABLESTATE
typedef enum
{
OFF = 0,
ON = 1
} EnableState;
#endif
/*
* This section contains register addresses and bit masks for
* the device status registers.
*/
#define REG_DEV_STATUS 0
#define DEV_SYS_INIT_MASK 0x80
#define DEV_LOL_B_MASK 0x40
#define DEV_LOL_A_MASK 0x20
#define DEV_LOS_CLKIN_MASK 0x10
#define DEV_LOS_XTAL_MASK 0x08
#define DEV_REVID_MASK 0x03
#define REG_DEV_STICKY 1
#define DEV_STKY_SYS_INIT_MASK 0x80
#define DEV_STKY_LOL_B_MASK 0x40
#define DEV_STKY_LOL_A_MASK 0x20
#define DEV_STKY_LOS_CLKIN_MASK 0x10
#define DEV_STKY_LOS_XTAL_MASK 0x08
#define REG_INT_MASK 2
#define INT_MASK_SYS_INIT_MASK 0x80
#define INT_MASK_LOL_B_MASK 0x40
#define INT_MASK_LOL_A_MASK 0x20
#define INT_MASK_LOS_CLKIN_MASK 0x10
#define INT_MASK_LOS_XTAL_MASK 0x08
/*
* This section contains data structures for configuring the
* oscillator, VCXO and CLKIN section.
*/
#define REG_XTAL_CL 183
#define XTAL_CL_MASK 0xC0
#define PLL_CL_MASK 0x36
//this sets the crystal load capacitance
typedef enum
{
XTAL_Load_4_pF = 0x00,
XTAL_Load_6_pF = 0x40,
XTAL_Load_8_pF = 0x80,
XTAL_Load_10_pF = 0xC0
} Si5351_XTALLoadTypeDef;
//The following is an unexplained parameter. However someone from SiLabs called it "VCO load cap".
//Lower settings seem to be more stable on higher frequencies, higher settings are more stable on lower frequencies allowing to tune the PLL to <200 MHz.
typedef enum
{
PLL_Capacitive_Load_0 = 0,
PLL_Capacitive_Load_1 = 1,
PLL_Capacitive_Load_2 = 2
} Si5351_PLLCapacitiveLoadTypeDef;
#define REG_CLKIN_DIV 15
#define CLKIN_MASK 0xC0
//this sets the CLKIN pre-divider, after division, CLKIN should
//fall between 10-40 MHz
typedef enum
{
CLKINDiv_Div1 = 0x00,
CLKINDiv_Div2 = 0x40,
CLKINDiv_Div4 = 0x80,
CLKINDiv_Div8 = 0xC0
} Si5351_CLKINDivTypeDef;
#define REG_FANOUT_EN 187
#define FANOUT_CLKIN_EN_MASK 0x80
#define FANOUT_XO_EN_MASK 0x40
#define FANOUT_MS_EN_MASK 0x10
#define REG_VCXO_PARAM_0_7 162
#define REG_VCXO_PARAM_8_15 163
#define REG_VCXO_PARAM_16_21 164
#define VCXO_PARAM_16_21_MASK 0x3F
#define VCXO_PARAM_MASK 0x003FFFFF
#define APR_MINIMUM 30 //minimum pull range
#define APR_MAXIMUM 240 //maximum pull range
#define CLKIN_MINIMUM 10000 //minimum CLKIN frequency after division in kHz
#define CLKIN_MAXIMUM 40000 //maximum CLKIN frequency after division in kHz
typedef struct
{
Si5351_XTALLoadTypeDef OSC_XTAL_Load; //capacitive load of XTAL, 10pF by default
Si5351_CLKINDivTypeDef CLKIN_Div; //CLKIN predivision, input f to PLL must be 10-40 MHz
uint8_t VCXO_Pull_Range_ppm; //can range from +-30 ppm to 240ppm
} Si5351_OSCConfigTypeDef;
/*
* This section contains data structures for configuring the
* PLL (PLLA and PLLB)
*/
#define REG_PLL_CLOCK_SOURCE 15
#define PLLA_CLOCK_SOURCE_MASK 0x04
#define PLLB_CLOCK_SOURCE_MASK 0x08
//this selects the clock source for the PLL
typedef enum
{
PLL_Clock_Source_XTAL = 0x00,
PLL_Clock_Source_CLKIN = 0x0C //0x04 for PLLA, 0x08 for PLLB, use mask!
} Si5351_PLLClockSourceTypeDef;
#define REG_FB_INT 22
#define FB_INT_MASK 0x40
#define REG_PLL_RESET 177
#define PLLA_RESET_MASK 0x20
#define PLLB_RESET_MASK 0x80
#define REG_MSN_P1_0_7 30
#define REG_MSN_P1_8_15 29
#define REG_MSN_P1_16_17 28
#define MSN_P1_16_17_MASK 0x03
#define REG_MSN_P2_0_7 33
#define REG_MSN_P2_8_15 32
#define REG_MSN_P2_16_19 31
#define MSN_P2_16_19_MASK 0x0F
#define REG_MSN_P3_0_7 27
#define REG_MSN_P3_8_15 26
#define REG_MSN_P3_16_19 31
#define MSN_P3_16_19_MASK 0xF0
#define MSNA_MSNB_OFFSET 8
typedef struct
{
uint32_t PLL_Multiplier_Integer;
uint32_t PLL_Multiplier_Numerator;
uint32_t PLL_Multiplier_Denominator;
Si5351_PLLClockSourceTypeDef PLL_Clock_Source;
Si5351_PLLCapacitiveLoadTypeDef PLL_Capacitive_Load;
} Si5351_PLLConfigTypeDef;
/*
* This section contains data structures for configuring the
* Spread Spectrum feature.
*/
#define REG_SSC_MODE 151
#define SSC_MODE_MASK 0x80
//this selects the Spread Spectrum mode
typedef enum
{
SS_Mode_DownSpread = 0x00,
SS_Mode_CenterSpread = 0x80
} Si5351_SSModeTypeDef;
typedef enum
{
SS_NCLK_0 = 0x00,
SS_NCLK_1 = 0x10,
SS_NCLK_2 = 0x20,
SS_NCLK_3 = 0x30,
SS_NCLK_4 = 0x40,
SS_NCLK_5 = 0x50,
SS_NCLK_6 = 0x60,
SS_NCLK_7 = 0x70,
SS_NCLK_8 = 0x80,
SS_NCLK_9 = 0x90,
SS_NCLK_10 = 0xA0,
SS_NCLK_11 = 0xB0,
SS_NCLK_12 = 0xC0,
SS_NCLK_13 = 0xD0,
SS_NCLK_14 = 0xE0,
SS_NCLK_15 = 0xF0
} Si5351_SSNCLKTypeDef;
#define REG_SSDN_P1_0_7 153
#define REG_SSDN_P1_8_11 154
#define SSDN_P1_8_11_MASK 0x0F
#define REG_SSDN_P2_0_7 150
#define REG_SSDN_P2_8_14 149
#define SSDN_P2_8_14_MASK 0x7F
#define REG_SSDN_P3_0_7 152
#define REG_SSDN_P3_8_14 151
#define SSDN_P3_8_14_MASK 0x7F
#define REG_SSUDP_0_7 155
#define REG_SSUDP_8_11 154
#define SSUDP_8_11_MASK 0xF0
#define REG_SSUP_P1_0_7 160
#define REG_SSUP_P1_8_11 161
#define SSUP_P1_8_11_MASK 0x0F
#define REG_SSUP_P2_0_7 157
#define REG_SSUP_P2_8_14 156
#define SSUP_P2_8_14_MASK 0x7F
#define REG_SSUP_P3_0_7 159
#define REG_SSUP_P3_8_14 158
#define SSUP_P3_8_14_MASK 0x7F
#define REG_SSC_EN 149
#define SSC_EN_MASK 0x80
#define REG_SS_NCLK 161
#define SS_NCLK_MASK 0xF0
typedef struct
{
uint32_t SS_Amplitude_ppm; //amplitude of the SS feature in ppm of center frequency
EnableState SS_Enable;
Si5351_SSModeTypeDef SS_Mode;
Si5351_SSNCLKTypeDef SS_NCLK;
} Si5351_SSConfigTypeDef;
/*
* This section contains data structures for configuring the
* Output Multisynth.
*/
//this selects the Multisynth clock source
typedef enum
{
MS_Clock_Source_PLLA = 0x00,
MS_Clock_Source_PLLB = 0x20
} Si5351_MSClockSourceTypeDef;
#define REG_MS_P1_0_7 46
#define REG_MS_P1_8_15 45
#define REG_MS_P1_16_17 44
#define MS_P1_16_17_MASK 0x03
#define REG_MS_P2_0_7 49
#define REG_MS_P2_8_15 48
#define REG_MS_P2_16_19 47
#define MS_P2_16_19_MASK 0x0F
#define REG_MS_P3_0_7 43
#define REG_MS_P3_8_15 42
#define REG_MS_P3_16_19 47
#define MS_P3_16_19_MASK 0xF0
#define REG_MS67_P1 90
#define REG_MS_INT 16
#define MS_INT_MASK 0x40
#define REG_MS_DIVBY4 44
#define MS_DIVBY4_MASK 0x0C
#define REG_MS_SRC 16
#define MS_SRC_MASK 0x20
#define MS_SETUP_STEP 1
#define MS_DIVIDER_STEP 8
typedef struct
{
Si5351_MSClockSourceTypeDef MS_Clock_Source; //select source on MS input
uint32_t MS_Divider_Integer; //the integer part of divider, called "a"
uint32_t MS_Divider_Numerator; //the numerator, called "b"
uint32_t MS_Divider_Denominator; //the denominator, called "c"
} Si5351_MSConfigTypeDef; //sets MS divider ( a+(b/c) ) and clock (PLLA/PLLB)
/*
* This section contains data structures for configuring the
* CLK, R divider and output stage (joined together because they make
* a tight block without any multiplexer).
*/
#define REG_CLK_SRC 16
#define CLK_SRC_MASK 0x0C
//this sets the CLK source clock
typedef enum
{
CLK_Clock_Source_XTAL = 0x00,
CLK_Clock_Source_CLKIN = 0x04,
CLK_Clock_Source_MS0_MS4 = 0x08, //this uses MS0 for CLK0..3 and MS4 for CLK4..7
CLK_Clock_Source_MS_Own = 0x0C //this uses MSx for CLKx
} Si5351_CLKClockSourceTypeDef; //configures multiplexer on CLK input
#define REG_CLK_R_DIV 44
#define CLK_R_DIV_MASK 0x70
#define REG_CLK_R67_DIV 92
#define CLK_R67_DIV_MASK 0x07
//this sets the R divider ratio
typedef enum
{
CLK_R_Div1 = 0x00,
CLK_R_Div2 = 0x10,
CLK_R_Div4 = 0x20,
CLK_R_Div8 = 0x30,
CLK_R_Div16 = 0x40,
CLK_R_Div32 = 0x50,
CLK_R_Div64 = 0x60,
CLK_R_Div128 = 0x70
} Si5351_CLKRDivTypeDef;
#define REG_CLK_DIS_STATE 24
#define CLK_DIS_STATE_MASK 0x03
//this sets output buffer behaviour when disabled
typedef enum
{
CLK_Disable_State_LOW = 0x00,
CLK_Disable_State_HIGH = 0x01,
CLK_Disable_State_HIGH_Z = 0x02, //three-stated when off
CLK_Disable_State_ALWAYS_ON = 0x03 //cannot be disabled
} Si5351_CLKDisableStateTypeDef;
#define REG_CLK_IDRV 16
#define CLK_IDRV_MASK 0x03
//this sets current drive of the output buffer
typedef enum
{
CLK_I_Drv_2mA = 0x00,
CLK_I_Drv_4mA = 0x01,
CLK_I_Drv_6mA = 0x02,
CLK_I_Drv_8mA = 0x03
} Si5351_CLKIDrvTypeDef;
#define REG_CLK_PHOFF 165
#define CLK_PHOFF_MASK 0x7F
#define REG_CLK_EN 3
#define REG_CLK_INV 16
#define CLK_INV_MASK 0x10
#define REG_CLK_PDN 16
#define CLK_PDN_MASK 0x80
#define REG_CLK_OEB 9
#define CLK_PHOFF_STEP 1
#define CLK_SETUP_STEP 1
#define CLK_R_DIV_STEP 8
typedef struct
{
Si5351_CLKClockSourceTypeDef CLK_Clock_Source; //clock source
/* this sets the time offset of the CLK channel, basic unit
* is one quarter of the VCO period (90deg offset),
* set it to 4*fVCO*toffset, the value is 7-bit, the max time offset
* varies between 35 and 53 ns (1 cycle for 28 and 19 MHz, respectively)
* according to the current frequency of the VCO
*/
uint8_t CLK_QuarterPeriod_Offset;
Si5351_CLKRDivTypeDef CLK_R_Div; //R divider value (only powers of 2)
EnableState CLK_Invert; //invert output clock
EnableState CLK_Enable; //enable flag
EnableState CLK_PowerDown; //powerdown flag
Si5351_CLKDisableStateTypeDef CLK_Disable_State; //sets output behaviour when disabled
Si5351_CLKIDrvTypeDef CLK_I_Drv; //output driver current drive strength
EnableState CLK_Use_OEB_Pin; //allows using OEB pin to enable clock
} Si5351_CLKConfigTypeDef;
/*
* This section contains main data structure for Si5351 configuration
*/
typedef struct
{
/*
* These are frequencies of the input clocks, set it in Hz.
*/
uint32_t f_XTAL;
uint32_t f_CLKIN;
//Interrupt masking - enabling it disables the int source from pulling INTR low
EnableState Interrupt_Mask_SysInit;
EnableState Interrupt_Mask_PLLB;
EnableState Interrupt_Mask_PLLA;
EnableState Interrupt_Mask_CLKIN;
EnableState Interrupt_Mask_XTAL;
//Fanout enable - enables internal clock routing
EnableState Fanout_MS_EN;
EnableState Fanout_XO_EN;
EnableState Fanout_CLKIN_EN;
I2C_TypeDef *I2Cx; //the I2C interface that will be used
uint8_t HW_I2C_Address; //I2C address of the Si5351 for the packages with A0 pin
//(also, some duds with strange address reported)
Si5351_OSCConfigTypeDef OSC; //Oscillator, CLKIN and VCXO settings
Si5351_PLLConfigTypeDef PLL[2]; //PLL settings for PLLA and PLLB
Si5351_MSConfigTypeDef MS[8]; //MultiSynth[0..7] settings
Si5351_CLKConfigTypeDef CLK[8]; //CLK[0..7], R divider and output stage settings
Si5351_SSConfigTypeDef SS; //spread spectrum settings
} Si5351_ConfigTypeDef;
/*
* Typedefs for selecting PLL, MS and CLK to be used
*/
//this selects PLL channel
typedef enum
{
PLL_A = 0,
PLL_B = 1
} Si5351_PLLChannelTypeDef;
//this selects Multisynth channel
typedef enum
{
MS0 = 0,
MS1 = 1,
MS2 = 2,
MS3 = 3,
MS4 = 4,
MS5 = 5,
MS6 = 6,
MS7 = 7
} Si5351_MSChannelTypeDef;
//this selects CLK channel
typedef enum
{
CLK0 = 0,
CLK1 = 1,
CLK2 = 2,
CLK3 = 3,
CLK4 = 4,
CLK5 = 5,
CLK6 = 6,
CLK7 = 7
} Si5351_CLKChannelTypeDef;
//this selects device status flag
typedef enum
{
StatusBit_SysInit = DEV_SYS_INIT_MASK,
StatusBit_PLLA = DEV_STKY_LOL_A_MASK,
StatusBit_PLLB = DEV_LOL_B_MASK,
StatusBit_CLKIN = DEV_LOS_CLKIN_MASK,
StatusBit_XTAL = DEV_LOS_XTAL_MASK,
} Si5351_StatusBitTypeDef;
//these write to and read from a Si5351 register, for porting
//purposes, these functions should be the only ones which should need edits
int Si5351_WriteRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address, uint8_t reg_data);
uint8_t Si5351_ReadRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address);
void Si5351_StructInit(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_OSCConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
EnableState Si5351_CheckStatusBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
EnableState Si5351_CheckStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
void Si5351_InterruptConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_ClearStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit);
void Si5351_PLLConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel);
void Si5351_PLLReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel);
void Si5351_PLLSimultaneousReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_SSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
void Si5351_MSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_MSChannelTypeDef MS_Channel);
void Si5351_CLKPowerCmd(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel);
void Si5351_CLKConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel);
int Si5351_Init(Si5351_ConfigTypeDef *Si5351_ConfigStruct);
#endif /* SI5351_H_ */

482
Core/Inc/stm32l4xx_hal_conf.h Normal file
View File

@ -0,0 +1,482 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l4xx_hal_conf.h.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CONF_H
#define STM32L4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_EXTI_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/**
* @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE 2097000U /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Register callback feature configuration ############### */
/**
* @brief Set below the peripheral configuration to "1U" to add the support
* of HAL callback registration/deregistration feature for the HAL
* driver(s). This allows user application to provide specific callback
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
* the default weak callback functions (see each stm32l4xx_hal_ppp.h file
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
* for each PPP peripheral).
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
#define USE_HAL_SD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U
#define USE_HAL_UART_REGISTER_CALLBACKS 0U
#define USE_HAL_USART_REGISTER_CALLBACKS 0U
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "Legacy/stm32l4xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32l4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32l4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
#include "stm32l4xx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32l4xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_CONF_H */

65
Core/Inc/stm32l4xx_it.h Normal file
View File

@ -0,0 +1,65 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void TIM1_UP_TIM16_IRQHandler(void);
void LPUART1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_IT_H */

59
Core/Src/freertos.c Normal file
View File

@ -0,0 +1,59 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : freertos.c
* Description : Code for freertos applications
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "FreeRTOS.h"
#include "task.h"
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN Variables */
/* USER CODE END Variables */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN FunctionPrototypes */
/* USER CODE END FunctionPrototypes */
/* Private application code --------------------------------------------------*/
/* USER CODE BEGIN Application */
/* USER CODE END Application */

663
Core/Src/main.c Normal file
View File

@ -0,0 +1,663 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "cmsis_os.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <stdio.h>
#include "at1_defines.h"
#include "stm32_si5351.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
I2C_HandleTypeDef hi2c1;
UART_HandleTypeDef hlpuart1;
PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* Definitions for defaultTask */
osThreadId_t defaultTaskHandle;
const osThreadAttr_t defaultTask_attributes = {
.name = "defaultTask",
.stack_size = 128 * 4,
.priority = (osPriority_t) osPriorityNormal,
};
/* Definitions for terminalTask */
osThreadId_t terminalTaskHandle;
const osThreadAttr_t terminalTask_attributes = {
.name = "terminalTask",
.stack_size = 128 * 4,
.priority = (osPriority_t) osPriorityBelowNormal,
};
/* Definitions for idTask */
osThreadId_t idTaskHandle;
const osThreadAttr_t idTask_attributes = {
.name = "idTask",
.stack_size = 128 * 4,
.priority = (osPriority_t) osPriorityLow,
};
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_LPUART1_UART_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void);
static void MX_I2C1_Init(void);
void StartDefaultTask(void *argument);
void start_terminal_task(void *argument);
void start_id_task(void *argument);
/* USER CODE BEGIN PFP */
// redirect the output of the printf function to the USART print function
// is calling fputc to transmit the output via the USART.
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_LPUART1_UART_Init();
MX_USB_OTG_FS_PCD_Init();
MX_I2C1_Init();
/* USER CODE BEGIN 2 */
si5351_inst_t instance_si5351[3] = {0};
// 1st SI5351 chip and with an A0 = 0:
instance_si5351[0] = si5351_init(&hi2c1, 27000000, 0x61);
// 2nd SI5351 chip on the same I2C bus "hi2c1" but address line A0 = 1
instance_si5351[1] = si5351_init(&hi2c1, 27000000, 0x60);
// 3rd SI5351 chip on another IC2 bus with handle "hi2c2" *\/
instance_si5351[2] = si5351_init(&hi2c1, 25000000, 0x60);
for (int i=0; i<3 ;i++) {
int ready;
ready = si5351_isready(instance_si5351[i]);
printf("Device No. %d (Instance No: 0x%x) is %s\n", i, (unsigned int) instance_si5351[i], (ready==0) ? "ready" : "N/A");
}
for (int i=2; i>=0; i--) {
si5351_deinit(instance_si5351[i]);
}
/* USER CODE END 2 */
/* Init scheduler */
osKernelInitialize();
/* USER CODE BEGIN RTOS_MUTEX */
/* add mutexes, ... */
/* USER CODE END RTOS_MUTEX */
/* USER CODE BEGIN RTOS_SEMAPHORES */
/* add semaphores, ... */
/* USER CODE END RTOS_SEMAPHORES */
/* USER CODE BEGIN RTOS_TIMERS */
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* USER CODE BEGIN RTOS_QUEUES */
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* creation of defaultTask */
defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
/* creation of terminalTask */
terminalTaskHandle = osThreadNew(start_terminal_task, NULL, &terminalTask_attributes);
/* creation of idTask */
idTaskHandle = osThreadNew(start_id_task, NULL, &idTask_attributes);
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* USER CODE BEGIN RTOS_EVENTS */
/* add events, ... */
/* USER CODE END RTOS_EVENTS */
/* Start scheduler */
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
Error_Handler();
}
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = 0;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 71;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV6;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
/** Enable MSI Auto calibration
*/
HAL_RCCEx_EnableMSIPLLMode();
}
/**
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
/* USER CODE BEGIN I2C1_Init 0 */
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
hi2c1.Init.Timing = 0x00505B89;
hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c1.Init.OwnAddress2 = 0;
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
{
Error_Handler();
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
{
Error_Handler();
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
/**
* @brief LPUART1 Initialization Function
* @param None
* @retval None
*/
static void MX_LPUART1_UART_Init(void)
{
/* USER CODE BEGIN LPUART1_Init 0 */
/* USER CODE END LPUART1_Init 0 */
/* USER CODE BEGIN LPUART1_Init 1 */
/* USER CODE END LPUART1_Init 1 */
hlpuart1.Instance = LPUART1;
hlpuart1.Init.BaudRate = 115200;
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
hlpuart1.Init.StopBits = UART_STOPBITS_1;
hlpuart1.Init.Parity = UART_PARITY_NONE;
hlpuart1.Init.Mode = UART_MODE_TX_RX;
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
}
/**
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
/* USER CODE BEGIN USB_OTG_FS_Init 0 */
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
hpcd_USB_OTG_FS.Init.battery_charging_enable = ENABLE;
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE;
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
HAL_PWREx_EnableVddIO2();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD1_GPIO_Port, LD1_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : PE2 PE3 PE4 PE5
PE6 PE7 PE8 PE9
PE10 PE11 PE12 PE13
PE14 PE15 PE0 PE1 */
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9
|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13
|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PF0 PF1 PF2 PF3
PF4 PF5 PF6 PF7
PF8 PF9 PF10 PF11
PF12 PF13 PF14 PF15 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7
|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/*Configure GPIO pins : PH0 PH3 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
/*Configure GPIO pins : PC0 PC1 PC2 PC3
PC4 PC5 PC6 PC8
PC9 PC10 PC11 PC12 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pins : PA0 PA1 PA2 PA3
PA4 PA5 PA6 PA7
PA15 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7
|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : PB0 PB1 PB2 PB10
PB11 PB12 PB13 PB15
PB4 PB5 PB6 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_15
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : PG0 PG1 PG2 PG3
PG4 PG9 PG10 PG11
PG12 PG13 PG14 PG15 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/*Configure GPIO pins : LD3_Pin LD2_Pin */
GPIO_InitStruct.Pin = LD3_Pin|LD2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : PD8 PD9 PD10 PD11
PD12 PD13 PD14 PD15
PD0 PD1 PD2 PD3
PD4 PD5 PD6 PD7 */
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : USB_OverCurrent_Pin */
GPIO_InitStruct.Pin = USB_OverCurrent_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : USB_PowerSwitchOn_Pin */
GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : LD1_Pin */
GPIO_InitStruct.Pin = LD1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(LD1_GPIO_Port, &GPIO_InitStruct);
}
/* USER CODE BEGIN 4 */
/**
* @brief Retargets the C library printf function to the USART.
* @param None
* @retval None
*/
PUTCHAR_PROTOTYPE
{
/* Place your implementation of fputc here */
/* e.g. write a character to the USART1 and Loop until the end of transmission */
HAL_UART_Transmit(&hlpuart1, (uint8_t *)&ch, 1, 0xFFFF);
return ch;
}
/* USER CODE END 4 */
/* USER CODE BEGIN Header_StartDefaultTask */
/**
* @brief Function implementing the defaultTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
/* USER CODE BEGIN 5 */
/* Infinite loop */
for(;;)
{
// HAL_GPIO_TogglePin(LD1_GPIO_Port, LD1_Pin);
HAL_GPIO_WritePin(LD1_GPIO_Port, LD1_Pin, GPIO_PIN_SET);
osDelay(1);
HAL_GPIO_WritePin(LD1_GPIO_Port, LD1_Pin, GPIO_PIN_RESET);
osDelay(1999);
}
/* USER CODE END 5 */
}
/* USER CODE BEGIN Header_start_terminal_task */
/**
* @brief Function implementing the terminalTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_start_terminal_task */
void start_terminal_task(void *argument)
{
/* USER CODE BEGIN start_terminal_task */
/* Infinite loop */
for(;;)
{
osDelay(1);
}
/* USER CODE END start_terminal_task */
}
/* USER CODE BEGIN Header_start_id_task */
/**
* @brief Function implementing the idTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_start_id_task */
void start_id_task(void *argument)
{
/* USER CODE BEGIN start_id_task */
//uint8_t tx_buf[80];
//int tx_buf_len;
/* check if the SI5351 is present */
int status = HAL_I2C_IsDeviceReady(&hi2c1, SI5351_I2C_ADDR, 3, 10 /*HAL_MAX_DELAY*/ ); // HAL_MAX_DELAY is blocking, use 10 ms
/* Infinite loop */
for(;;)
{
printf("\n" PROGRAM_ID "\n");
printf(AUTHOR_STRING "\n");
if (status == HAL_OK) {
printf("Si5351 device found.\n");
} else {
printf("Error: Could not detect Si5351 device.\n");
}
osDelay(30*60);
}
/* USER CODE END start_id_task */
}
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM16 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM16) {
HAL_IncTick();
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

889
Core/Src/si5351.c Normal file
View File

@ -0,0 +1,889 @@
/*
* si5351.c
*
* Created on: Jan 14, 2019
* Author: Petr Polasek
*
* To make this library useable on any other device than
* STM32Fxxx Cortex Mx, please edit these parts of the library:
*
* DEFINES:
* SI5351_I2C_PERIPHERAL - the I2C peripheral name according
* to your devices HAL library
* I2C_TIMEOUT - time for the communication to time out
*
* TYPEDEFS:
* Si5351_ConfigTypeDef - the I2Cx parameter should be changed
* so that its type corresponds to your HAL library
*
* FUNCTIONS:
* Si5351_WriteRegister
* Si5351_ReadRegister
* You need to write your own I2C handlers here
*
*/
//put your I2C HAL library name here
//#include "stm32f10x_i2c.h"
#include "stm32l4xx_hal.h"
#if 0
#include "si5351.h"
int Si5351_WriteRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address, uint8_t reg_data)
{
uint32_t error_wait;
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_BUSY) == SET)
{
error_wait--;
if (error_wait==0)
{
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, ENABLE);
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, DISABLE);
return 1;
}
}
//wait for I2C to get ready, if not ready in time, reset I2C and return
I2C_GenerateSTART(Si5351_ConfigStruct->I2Cx, ENABLE);
//send START condition
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_MODE_SELECT) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for START to be sent, if not sent in time, return
I2C_Send7bitAddress(Si5351_ConfigStruct->I2Cx, Si5351_ConfigStruct->HW_I2C_Address, I2C_Direction_Transmitter);
//send address+RW bit
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for address to be sent, if not sent in time, return
I2C_SendData(Si5351_ConfigStruct->I2Cx, reg_address);
//send reg address
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for reg address to be sent
I2C_SendData(Si5351_ConfigStruct->I2Cx, reg_data);
//send reg data
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for data to be sent, if not sent in time, return
I2C_GenerateSTOP(Si5351_ConfigStruct->I2Cx, ENABLE);
//generate STOP condition
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_STOPF))
{
error_wait--;
if (error_wait==0) return 1;
}
//wait until STOP is cleared
return 0;
}
uint8_t Si5351_ReadRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address)
{
uint32_t error_wait;
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_BUSY) == SET)
{
error_wait--;
if (error_wait==0)
{
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, ENABLE);
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, DISABLE);
return 1;
}
}
//wait for I2C to get ready, if not ready in time, reset I2C and return
I2C_GenerateSTART(Si5351_ConfigStruct->I2Cx, ENABLE);
//send START condition
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_MODE_SELECT) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for START to be sent, if not sent in time, return
I2C_Send7bitAddress(Si5351_ConfigStruct->I2Cx, Si5351_ConfigStruct->HW_I2C_Address, I2C_Direction_Transmitter);
//send address+RW bit
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for address to be sent, if not sent in time, return
I2C_SendData(Si5351_ConfigStruct->I2Cx, reg_address);
//send reg address
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for reg address to be sent
I2C_GenerateSTOP(Si5351_ConfigStruct->I2Cx, ENABLE);
//generate STOP condition
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_STOPF))
{
error_wait--;
if (error_wait==0) return 1;
}
//wait until STOP is cleared
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_BUSY) == SET)
{
error_wait--;
if (error_wait==0)
{
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, ENABLE);
I2C_SoftwareResetCmd(Si5351_ConfigStruct->I2Cx, DISABLE);
return 1;
}
}
//wait for I2C to get ready, if not ready in time, reset I2C and return
I2C_GenerateSTART(Si5351_ConfigStruct->I2Cx, ENABLE);
//send START condition
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_MODE_SELECT) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for START to be sent, if not sent in time, return
I2C_Send7bitAddress(Si5351_ConfigStruct->I2Cx, Si5351_ConfigStruct->HW_I2C_Address, I2C_Direction_Receiver);
//send address+RW bit
error_wait = I2C_TIMEOUT;
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for address to be sent, if not sent in time, return
while (I2C_CheckEvent(Si5351_ConfigStruct->I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED) == ERROR)
{
error_wait--;
if (error_wait==0) return 1;
}
//wait for data
uint8_t reg_data;
reg_data = I2C_ReceiveData(Si5351_ConfigStruct->I2Cx);
//receive reg data
I2C_GenerateSTOP(Si5351_ConfigStruct->I2Cx, ENABLE);
//generate STOP condition
error_wait = I2C_TIMEOUT;
while (I2C_GetFlagStatus(Si5351_ConfigStruct->I2Cx, I2C_FLAG_STOPF))
{
error_wait--;
if (error_wait==0) return 1;
}
//wait until STOP is cleared
return reg_data;
}
//set safe values in the config structure
void Si5351_StructInit(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint8_t i;
Si5351_ConfigStruct->HW_I2C_Address = SI5351_I2C_ADDRESS;
Si5351_ConfigStruct->I2Cx = SI5351_I2C_PERIPHERAL;
Si5351_ConfigStruct->f_CLKIN = SI5351_CLKIN_FREQ;
Si5351_ConfigStruct->f_XTAL = SI5351_XTAL_FREQ;
Si5351_ConfigStruct->Interrupt_Mask_CLKIN = ON;
Si5351_ConfigStruct->Interrupt_Mask_PLLA = ON;
Si5351_ConfigStruct->Interrupt_Mask_PLLB = ON;
Si5351_ConfigStruct->Interrupt_Mask_SysInit = ON;
Si5351_ConfigStruct->Interrupt_Mask_XTAL = ON;
Si5351_ConfigStruct->Fanout_CLKIN_EN = ON;
Si5351_ConfigStruct->Fanout_MS_EN = ON;
Si5351_ConfigStruct->Fanout_XO_EN = ON;
Si5351_ConfigStruct->OSC.CLKIN_Div = CLKINDiv_Div1;
Si5351_ConfigStruct->OSC.OSC_XTAL_Load = XTAL_Load_10_pF;
Si5351_ConfigStruct->OSC.VCXO_Pull_Range_ppm = 0; //maybe should be set to 30 ppm, not clear from the AN-619
for (i=0; i<=1; i++)
{
Si5351_ConfigStruct->PLL[i].PLL_Clock_Source = PLL_Clock_Source_XTAL;
Si5351_ConfigStruct->PLL[i].PLL_Multiplier_Integer = 32; //range 24..36 for 25 MHz clock
Si5351_ConfigStruct->PLL[i].PLL_Multiplier_Numerator = 0; //range 0..1048575
Si5351_ConfigStruct->PLL[i].PLL_Multiplier_Denominator = 1; //range 1..1048575
Si5351_ConfigStruct->PLL[i].PLL_Capacitive_Load = PLL_Capacitive_Load_0; //select 0, unless you want to tune the PLL to <200 MHZ
}
Si5351_ConfigStruct->SS.SS_Amplitude_ppm = 0; //1.5% modulation = 15000
Si5351_ConfigStruct->SS.SS_Enable = OFF;
Si5351_ConfigStruct->SS.SS_Mode = SS_Mode_CenterSpread;
Si5351_ConfigStruct->SS.SS_NCLK = SS_NCLK_0; //default value, this parameter is unexplained in documentation
for (i=0; i<=7; i++)
{
Si5351_ConfigStruct->MS[i].MS_Clock_Source = MS_Clock_Source_PLLA;
Si5351_ConfigStruct->MS[i].MS_Divider_Integer = 4;
Si5351_ConfigStruct->MS[i].MS_Divider_Numerator = 0;
Si5351_ConfigStruct->MS[i].MS_Divider_Denominator = 1;
Si5351_ConfigStruct->CLK[i].CLK_Clock_Source = CLK_Clock_Source_MS_Own;
Si5351_ConfigStruct->CLK[i].CLK_Disable_State = CLK_Disable_State_HIGH_Z;
Si5351_ConfigStruct->CLK[i].CLK_Enable = OFF;
Si5351_ConfigStruct->CLK[i].CLK_I_Drv = CLK_I_Drv_8mA;
Si5351_ConfigStruct->CLK[i].CLK_Invert = OFF;
Si5351_ConfigStruct->CLK[i].CLK_PowerDown = OFF;
Si5351_ConfigStruct->CLK[i].CLK_QuarterPeriod_Offset = 0;
Si5351_ConfigStruct->CLK[i].CLK_R_Div = CLK_R_Div1;
Si5351_ConfigStruct->CLK[i].CLK_Use_OEB_Pin = OFF;
}
}
void Si5351_OSCConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint8_t tmp;
uint32_t VCXO_Param;
//set XTAL capacitive load and PLL VCO load capacitance
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_XTAL_CL);
tmp &= ~(XTAL_CL_MASK | PLL_CL_MASK);
tmp |= (XTAL_CL_MASK & (Si5351_ConfigStruct->OSC.OSC_XTAL_Load)) | (PLL_CL_MASK & ((Si5351_ConfigStruct->PLL[0].PLL_Capacitive_Load) << 1)) | (PLL_CL_MASK & ((Si5351_ConfigStruct->PLL[1].PLL_Capacitive_Load) << 4));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_XTAL_CL, tmp);
//set CLKIN pre-divider
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLKIN_DIV);
tmp &= ~CLKIN_MASK;
tmp |= CLKIN_MASK & Si5351_ConfigStruct->OSC.CLKIN_Div;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLKIN_DIV, tmp);
//set fanout of XO, MS0, MS4 and CLKIN - should be always on unless you
//need to reduce power consumption
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_FANOUT_EN);
tmp &= ~(FANOUT_CLKIN_EN_MASK | FANOUT_MS_EN_MASK | FANOUT_XO_EN_MASK);
if (Si5351_ConfigStruct->Fanout_CLKIN_EN == ON) tmp |= FANOUT_CLKIN_EN_MASK;
if (Si5351_ConfigStruct->Fanout_MS_EN == ON) tmp |= FANOUT_MS_EN_MASK;
if (Si5351_ConfigStruct->Fanout_XO_EN == ON) tmp |= FANOUT_XO_EN_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_FANOUT_EN, tmp);
//if "b" in PLLB set to 10^6, set VCXO parameter
if (Si5351_ConfigStruct->PLL[1].PLL_Multiplier_Denominator == 1000000)
{
VCXO_Param = VCXO_PARAM_MASK & (uint32_t)
((103 * Si5351_ConfigStruct->OSC.VCXO_Pull_Range_ppm
* ((uint64_t)128000000 * Si5351_ConfigStruct->PLL[1].PLL_Multiplier_Integer +
Si5351_ConfigStruct->PLL[1].PLL_Multiplier_Numerator))/100000000);
} else {
VCXO_Param = 0;
}
tmp = (uint8_t) VCXO_Param;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_VCXO_PARAM_0_7, tmp);
tmp = (uint8_t)(VCXO_Param>>8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_VCXO_PARAM_8_15, tmp);
tmp = (uint8_t)((VCXO_Param>>16) & VCXO_PARAM_16_21_MASK);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_VCXO_PARAM_16_21, tmp);
}
EnableState Si5351_CheckStatusBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit)
{
uint8_t tmp;
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_DEV_STATUS);
tmp &= StatusBit;
return tmp;
}
EnableState Si5351_CheckStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit)
{
uint8_t tmp;
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_DEV_STICKY);
tmp &= StatusBit;
return tmp;
}
void Si5351_InterruptConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint8_t tmp;
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_INT_MASK);
tmp &= ~INT_MASK_LOS_XTAL_MASK;
if (Si5351_ConfigStruct->Interrupt_Mask_XTAL == ON)
{
tmp |= INT_MASK_LOS_XTAL_MASK;
}
tmp &= ~INT_MASK_LOS_CLKIN_MASK;
if (Si5351_ConfigStruct->Interrupt_Mask_CLKIN == ON)
{
tmp |= INT_MASK_LOS_CLKIN_MASK;
}
tmp &= ~INT_MASK_LOL_A_MASK;
if (Si5351_ConfigStruct->Interrupt_Mask_PLLA == ON)
{
tmp |= INT_MASK_LOL_A_MASK;
}
tmp &= ~INT_MASK_LOL_B_MASK;
if (Si5351_ConfigStruct->Interrupt_Mask_PLLB == ON)
{
tmp |= INT_MASK_LOL_B_MASK;
}
tmp &= ~INT_MASK_SYS_INIT_MASK;
if (Si5351_ConfigStruct->Interrupt_Mask_SysInit == ON)
{
tmp |= INT_MASK_SYS_INIT_MASK;
}
Si5351_WriteRegister(Si5351_ConfigStruct, REG_INT_MASK, tmp);
}
void Si5351_ClearStickyBit(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_StatusBitTypeDef StatusBit)
{
uint8_t tmp;
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_DEV_STICKY);
tmp &= ~StatusBit;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_DEV_STICKY, tmp);
}
void Si5351_PLLConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel)
{
uint8_t tmp, tmp_mask;
uint32_t MSN_P1, MSN_P2, MSN_P3;
//set PLL clock source
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_PLL_CLOCK_SOURCE);
tmp_mask = PLLA_CLOCK_SOURCE_MASK << PLL_Channel;
tmp &= ~tmp_mask;
tmp |= tmp_mask & Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Clock_Source;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_PLL_CLOCK_SOURCE, tmp);
//if new multiplier not even integer, disable the integer mode
if ((Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Numerator != 0) | ((Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Integer & 0x01) != 0 ))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_FB_INT + PLL_Channel);
tmp &= ~FB_INT_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_FB_INT + PLL_Channel, tmp);
}
//configure the PLL multiplier
MSN_P1 = 128 * Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Integer + ((128 * Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Numerator) / Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Denominator) - 512;
MSN_P2 = 128 * Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Numerator - Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Denominator * ((128 * Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Numerator) / Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Denominator);
MSN_P3 = Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Denominator;
tmp = (uint8_t) MSN_P1;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P1_0_7 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) (MSN_P1 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P1_8_15 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) (MSN_P1_16_17_MASK & (MSN_P1 >> 16));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P1_16_17 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) MSN_P2;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P2_0_7 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) (MSN_P2 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P2_8_15 + 8 * PLL_Channel, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MSN_P2_16_19);
tmp &= ~MSN_P2_16_19_MASK;
tmp |= (uint8_t) (MSN_P2_16_19_MASK & (MSN_P2 >> 16));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P2_16_19 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) MSN_P3;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P3_0_7 + 8 * PLL_Channel, tmp);
tmp = (uint8_t) (MSN_P3 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P3_8_15 + 8 * PLL_Channel, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MSN_P3_16_19);
tmp &= ~MSN_P3_16_19_MASK;
tmp |= (uint8_t) (MSN_P3_16_19_MASK & ((MSN_P3 >> 16) << 4));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MSN_P3_16_19 + 8 * PLL_Channel, tmp);
//if new multiplier is an even integer, enable integer mode
if ((Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Numerator == 0) & ((Si5351_ConfigStruct->PLL[PLL_Channel].PLL_Multiplier_Integer & 0x01) == 0 ))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_FB_INT + PLL_Channel);
tmp |= FB_INT_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_FB_INT + PLL_Channel, tmp);
}
}
void Si5351_PLLReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_PLLChannelTypeDef PLL_Channel)
{
uint8_t tmp;
//reset PLL
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_PLL_RESET);
if (PLL_Channel == PLL_A)
{
tmp |= PLLA_RESET_MASK;
} else {
tmp |= PLLB_RESET_MASK;
}
Si5351_WriteRegister(Si5351_ConfigStruct, REG_PLL_RESET, tmp);
}
void Si5351_PLLSimultaneousReset(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint8_t tmp;
//reset PLL
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_PLL_RESET);
tmp |= PLLA_RESET_MASK | PLLB_RESET_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_PLL_RESET, tmp);
}
void Si5351_SSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint8_t tmp;
uint32_t SSUDP, SSUP_P1, SSUP_P2, SSUP_P3, SSDN_P1, SSDN_P2, SSDN_P3;
uint64_t SSDN, SSUP;
//turn off SS if it should be disabled
if ((Si5351_ConfigStruct->SS.SS_Enable == OFF)|
(((Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Integer & 0x01) == 0)
& (Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Numerator == 0)) )
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSC_EN);
tmp &= ~SSC_EN_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSC_EN, tmp);
}
//set default value of SS_NCLK - spread spectrum reserved register
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SS_NCLK);
tmp &= ~SS_NCLK_MASK;
tmp |= SS_NCLK_MASK & (Si5351_ConfigStruct->SS.SS_NCLK);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SS_NCLK, tmp);
//set SS mode
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSC_MODE);
tmp &= ~SSC_MODE_MASK;
tmp |= SSC_MODE_MASK & Si5351_ConfigStruct->SS.SS_Mode;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSC_MODE, tmp);
//set SSUDP parameter
if (Si5351_ConfigStruct->PLL[0].PLL_Clock_Source == PLL_Clock_Source_CLKIN)
{
SSUDP = (Si5351_ConfigStruct->f_CLKIN)/(4*31500);
} else {
SSUDP = (Si5351_ConfigStruct->f_XTAL)/(4*31500);
}
//set SSUDP parameter
tmp = (uint8_t) SSUDP;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUDP_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSUDP_8_11);
tmp &= ~SSUDP_8_11_MASK;
tmp |= (uint8_t) (SSUDP_8_11_MASK & ((SSUDP >> 8) << 4));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUDP_8_11, tmp);
//calculate SSUP and SSDN parameters
if (Si5351_ConfigStruct->SS.SS_Mode == SS_Mode_CenterSpread)
{
SSUP = ((uint64_t)(64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Integer
+ (64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Numerator)/(Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Denominator)
) * Si5351_ConfigStruct->SS.SS_Amplitude_ppm
) / ((1000000 - Si5351_ConfigStruct->SS.SS_Amplitude_ppm) * SSUDP);
SSDN = ((uint64_t)(64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Integer
+ (64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Numerator)/(Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Denominator)
) * Si5351_ConfigStruct->SS.SS_Amplitude_ppm
) / ((1000000 + Si5351_ConfigStruct->SS.SS_Amplitude_ppm) * SSUDP);
SSUP_P1 = (uint32_t) (SSUP/1000000);
SSUP_P2 = (uint32_t)(32767*(SSUP/1000000-SSUP_P1));
SSUP_P3 = 0x7FFF;
} else {
SSDN = ((uint64_t)(64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Integer
+ (64000000*Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Numerator)/(Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Denominator)
) * Si5351_ConfigStruct->SS.SS_Amplitude_ppm
) / ((1000000 + Si5351_ConfigStruct->SS.SS_Amplitude_ppm) * SSUDP);
SSUP_P1 = 0;
SSUP_P2 = 0;
SSUP_P3 = 1;
}
//set SSDN parameter
SSDN_P1 = (uint32_t) (SSDN/1000000);
SSDN_P2 = (uint32_t)(32767*(SSDN/1000000-SSDN_P1));
SSDN_P3 = 0x7FFF;
//write SSUP parameter P1
tmp = (uint8_t) SSUP_P1;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P1_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSUP_P1_8_11);
tmp &= ~SSUP_P1_8_11_MASK;
tmp |= (uint8_t)(SSUP_P1_8_11_MASK & (SSUP_P1 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P1_8_11, tmp);
//write SSUP parameter P2
tmp = (uint8_t) SSUP_P2;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P2_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSUP_P2_8_14);
tmp &= ~SSUP_P2_8_14_MASK;
tmp |= (uint8_t)(SSUP_P2_8_14_MASK & (SSUP_P2 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P2_8_14, tmp);
//write SSUP parameter P3
tmp = (uint8_t) SSUP_P3;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P3_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSUP_P3_8_14);
tmp &= ~SSUP_P3_8_14_MASK;
tmp |= (uint8_t)(SSUP_P3_8_14_MASK & (SSUP_P3 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSUP_P3_8_14, tmp);
//write SSDN parameter P1
tmp = (uint8_t) SSDN_P1;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P1_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSDN_P1_8_11);
tmp &= ~SSDN_P1_8_11_MASK;
tmp |= (uint8_t)(SSDN_P1_8_11_MASK & (SSDN_P1 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P1_8_11, tmp);
//write SSDN parameter P2
tmp = (uint8_t) SSDN_P2;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P2_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSDN_P2_8_14);
tmp &= ~SSDN_P2_8_14_MASK;
tmp |= (uint8_t)(SSDN_P2_8_14_MASK & (SSDN_P2 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P2_8_14, tmp);
//write SSDN parameter P3
tmp = (uint8_t) SSDN_P3;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P3_0_7, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSDN_P3_8_14);
tmp &= ~SSDN_P3_8_14_MASK;
tmp |= (uint8_t)(SSDN_P3_8_14_MASK & (SSDN_P3 >> 8));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSDN_P3_8_14, tmp);
//turn on SS if it should be enabled
if ((Si5351_ConfigStruct->SS.SS_Enable == ON)
& (((Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Integer & 0x01) != 0)
| (Si5351_ConfigStruct->PLL[0].PLL_Multiplier_Numerator != 0)))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_SSC_EN);
tmp |= SSC_EN_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_SSC_EN, tmp);
}
}
void Si5351_MSConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_MSChannelTypeDef MS_Channel)
{
uint8_t tmp;
uint32_t MS_P1, MS_P2, MS_P3;
//configure MultiSynth clock source
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_SRC + MS_Channel);
tmp &= ~MS_SRC_MASK;
if (Si5351_ConfigStruct->MS[MS_Channel].MS_Clock_Source == MS_Clock_Source_PLLB)
{
tmp |= MS_SRC_MASK;
}
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_SRC + MS_Channel, tmp);
if (MS_Channel <= MS5) //configuration is simpler for MS6 and 7 since they are integer-only
{
//if next value not in even integer mode or if divider is not equal to 4, disable DIVBY4
if ((Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer != 4)|(Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator != 0))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_DIVBY4 + 8 * MS_Channel);
tmp &= ~MS_DIVBY4_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_DIVBY4 + 8 * MS_Channel, tmp);
}
//if next value not in even integer mode or SS enabled, disable integer mode
if ((Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator != 0)|((Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer & 0x01) != 0)|(Si5351_ConfigStruct->SS.SS_Enable == ON))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_INT + MS_Channel);
tmp &= ~MS_INT_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_INT + MS_Channel, tmp);
}
//set new divider value
MS_P1 = 128 * Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer
+ ((128 * Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator) / Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Denominator)
- 512;
MS_P2 = 128 * Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator
- Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Denominator
* ((128 * Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator) / Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Denominator);
MS_P3 = Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Denominator;
tmp = (uint8_t) MS_P1;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P1_0_7 + 8 * MS_Channel, tmp);
tmp = (uint8_t) (MS_P1 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P1_8_15 + 8 * MS_Channel, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_P1_16_17);
tmp &= ~MS_P1_16_17_MASK;
tmp |= (uint8_t) (MS_P1_16_17_MASK & (MS_P1 >> 16));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P1_16_17 + 8 * MS_Channel, tmp);
tmp = (uint8_t) MS_P2;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P2_0_7 + 8 * MS_Channel, tmp);
tmp = (uint8_t) (MS_P2 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P2_8_15 + 8 * MS_Channel, tmp);
Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_P2_16_19 + 8 * MS_Channel);
tmp &= ~MS_P2_16_19_MASK;
tmp |= (uint8_t) (MS_P2_16_19_MASK & (MS_P2 >> 16));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P2_16_19 + 8 * MS_Channel, tmp);
tmp = (uint8_t) MS_P3;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P3_0_7 + 8 * MS_Channel, tmp);
tmp = (uint8_t) (MS_P3 >> 8);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P3_8_15 + 8 * MS_Channel, tmp);
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_P3_16_19 + 8 * MS_Channel);
tmp &= ~MS_P3_16_19_MASK;
tmp |= (uint8_t) (MS_P3_16_19_MASK & ((MS_P3 >> 16) << 4));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_P3_16_19 + 8 * MS_Channel, tmp);
//if next value is even integer and SS not enabled, enable integer mode
if ((Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Numerator == 0) & ((Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer & 0x01) == 0) & (Si5351_ConfigStruct->SS.SS_Enable == OFF))
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_INT + MS_Channel);
tmp |= MS_INT_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_INT + MS_Channel, tmp);
//if next value in integer mode and if divider is equal to 4, enable DIVBY4
if (Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer == 4)
{
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_MS_DIVBY4 + 8 * MS_Channel);
tmp |= MS_DIVBY4_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS_DIVBY4 + 8 * MS_Channel, tmp);
}
}
} else {
//configure divider of Multisynth 6 and 7
Si5351_WriteRegister(Si5351_ConfigStruct, REG_MS67_P1 + (MS_Channel - MS6), (uint8_t)(Si5351_ConfigStruct->MS[MS_Channel].MS_Divider_Integer));
//can be only even integers between 6 and 254, inclusive
}
}
void Si5351_CLKPowerCmd(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel)
{
uint8_t tmp, tmp_mask;
//set CLK disable state
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_DIS_STATE + (CLK_Channel >> 2)); //increment the address by 1 if CLKx>=CLK4
tmp_mask = CLK_DIS_STATE_MASK << ((CLK_Channel & 0x03)<<1); //shift the mask according to the selected channel
tmp &= ~tmp_mask;
tmp |= tmp_mask & ((Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Disable_State) << ((CLK_Channel & 0x03)<<1));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_DIS_STATE + (CLK_Channel >> 2), tmp);
//set OEB pin
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_OEB);
tmp_mask = 1 << CLK_Channel;
tmp &= ~tmp_mask;
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Use_OEB_Pin == OFF)
{
tmp |= tmp_mask;
}
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Enable == OFF) //disable clock
{
//power down the clock
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_EN);
tmp |= 1 << CLK_Channel;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_EN, tmp);
}
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_PowerDown == ON) //power down clock
{
//power down output driver
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_PDN + CLK_Channel);
tmp |= CLK_PDN_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_PDN + CLK_Channel, tmp);
}
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_PowerDown == OFF) //power up clock
{
//power up output driver
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_PDN + CLK_Channel);
tmp &= ~CLK_PDN_MASK;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_PDN + CLK_Channel, tmp);
}
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Enable == ON) //enable clock
{
//power up the clock
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_EN);
tmp &= ~(1 << CLK_Channel);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_EN, tmp);
}
}
void Si5351_CLKConfig(Si5351_ConfigTypeDef *Si5351_ConfigStruct, Si5351_CLKChannelTypeDef CLK_Channel)
{
uint8_t tmp, tmp_mask;
//set CLK source clock
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_SRC + CLK_Channel);
tmp &= ~CLK_SRC_MASK;
tmp |= CLK_SRC_MASK & Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Clock_Source;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_SRC + CLK_Channel, tmp);
//set CLK inversion
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_INV + CLK_Channel);
tmp &= ~CLK_INV_MASK;
if (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_Invert == ON)
{
tmp |= CLK_INV_MASK;
}
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_INV + CLK_Channel, tmp);
//set CLK current drive
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_IDRV + CLK_Channel);
tmp &= ~CLK_IDRV_MASK;
tmp |= CLK_IDRV_MASK & Si5351_ConfigStruct->CLK[CLK_Channel].CLK_I_Drv;
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_IDRV + CLK_Channel, tmp);
if (CLK_Channel <= CLK5) //CLK6 and 7 are integer only, which causes several limitations
{
//set CLK phase offset
tmp = CLK_PHOFF_MASK & (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_QuarterPeriod_Offset);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_PHOFF + CLK_Channel, tmp);
//set Rx divider
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_R_DIV + CLK_Channel * CLK_R_DIV_STEP);
tmp &= ~CLK_R_DIV_MASK;
tmp |= CLK_R_DIV_MASK & (Si5351_ConfigStruct->CLK[CLK_Channel].CLK_R_Div);
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_R_DIV + CLK_Channel * CLK_R_DIV_STEP, tmp);
} else {
//CLK6 and CLK7 have no fractional mode, so they lack the phase offset function
//set Rx divider
tmp_mask = CLK_R67_DIV_MASK << ((CLK_Channel-CLK6) << 2); //shift mask left by 4 if CLK7
tmp = Si5351_ReadRegister(Si5351_ConfigStruct, REG_CLK_R67_DIV);
tmp &= ~tmp_mask;
tmp |= tmp_mask & ((Si5351_ConfigStruct->CLK[CLK_Channel].CLK_R_Div >> 4) << ((CLK_Channel-CLK6) << 2));
Si5351_WriteRegister(Si5351_ConfigStruct, REG_CLK_R67_DIV, tmp);
}
}
int Si5351_Init(Si5351_ConfigTypeDef *Si5351_ConfigStruct)
{
uint32_t timeout = SI5351_TIMEOUT;
uint8_t i;
//wait for the 5351 to initialize
while (Si5351_CheckStatusBit(Si5351_ConfigStruct, StatusBit_SysInit))
{
timeout--;
if (timeout==0) return 1; //return 1 if initialization timed out
}
//configure oscillator, fanout, interrupts, VCXO
Si5351_OSCConfig(Si5351_ConfigStruct);
Si5351_InterruptConfig(Si5351_ConfigStruct);
//configure PLLs
for (i=PLL_A; i<=PLL_B; i++)
{
Si5351_PLLConfig(Si5351_ConfigStruct, i);
Si5351_PLLReset(Si5351_ConfigStruct, i);
}
//configure Spread Spectrum
Si5351_SSConfig(Si5351_ConfigStruct);
//Configure Multisynths
for (i=MS0; i<=MS7; i++)
{
Si5351_MSConfig(Si5351_ConfigStruct, i);
}
//configure outputs
for (i=CLK0; i<=CLK7; i++)
{
Si5351_CLKConfig(Si5351_ConfigStruct, i);
}
//wait for PLLs to lock
while (Si5351_CheckStatusBit(Si5351_ConfigStruct, StatusBit_SysInit | StatusBit_PLLA | StatusBit_PLLB))
{
timeout--;
if (timeout==0) return 1; //return 1 if problem with any PLL
}
//clear sticky bits
Si5351_ClearStickyBit(Si5351_ConfigStruct, StatusBit_SysInit | StatusBit_PLLA | StatusBit_PLLB);
if (Si5351_ConfigStruct->f_CLKIN != 0) //if CLKIN used, check it as well
{
while (Si5351_CheckStatusBit(Si5351_ConfigStruct, StatusBit_CLKIN))
{
timeout--;
if (timeout==0) return 1; //return 1 if initialization timed out
}
//clear CLKIN sticky bit
Si5351_ClearStickyBit(Si5351_ConfigStruct, StatusBit_CLKIN);
}
if (Si5351_ConfigStruct->f_XTAL != 0) //if XTAL used, check it as well
{
while (Si5351_CheckStatusBit(Si5351_ConfigStruct, StatusBit_XTAL))
{
timeout--;
if (timeout==0) return 1; //return 1 if initialization timed out
}
//clear XTAL sticky bit
Si5351_ClearStickyBit(Si5351_ConfigStruct, StatusBit_XTAL);
}
//power on or off the outputs
for (i=CLK0; i<=CLK7; i++)
{
Si5351_CLKPowerCmd(Si5351_ConfigStruct, i);
}
return 0;
}
#endif

1025
Core/Src/stm32_si5351.c Normal file
View File

File diff suppressed because it is too large Load Diff

359
Core/Src/stm32l4xx_hal_msp.c Normal file
View File

@ -0,0 +1,359 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief I2C MSP Initialization
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
/**
* @brief I2C MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
if(hi2c->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C1_CLK_DISABLE();
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
/* USER CODE BEGIN I2C1_MspDeInit 1 */
/* USER CODE END I2C1_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
HAL_PWREx_EnableVddIO2();
/**LPUART1 GPIO Configuration
PG7 ------> LPUART1_TX
PG8 ------> LPUART1_RX
*/
GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/* LPUART1 interrupt Init */
HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(LPUART1_IRQn);
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspDeInit 0 */
/* USER CODE END LPUART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LPUART1_CLK_DISABLE();
/**LPUART1 GPIO Configuration
PG7 ------> LPUART1_TX
PG8 ------> LPUART1_RX
*/
HAL_GPIO_DeInit(GPIOG, STLK_RX_Pin|STLK_TX_Pin);
/* LPUART1 interrupt DeInit */
HAL_NVIC_DisableIRQ(LPUART1_IRQn);
/* USER CODE BEGIN LPUART1_MspDeInit 1 */
/* USER CODE END LPUART1_MspDeInit 1 */
}
}
/**
* @brief PCD MSP Initialization
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USB_OTG_FS GPIO Configuration
PA8 ------> USB_OTG_FS_SOF
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = USB_VBUS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
/* Enable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSB();
__HAL_RCC_PWR_CLK_DISABLE();
}
else
{
HAL_PWREx_EnableVddUSB();
}
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
/**
* @brief PCD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
{
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
/* USER CODE END USB_OTG_FS_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
/**USB_OTG_FS GPIO Configuration
PA8 ------> USB_OTG_FS_SOF
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin
|USB_DP_Pin);
/* Disable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_DisableVddUSB();
__HAL_RCC_PWR_CLK_DISABLE();
}
else
{
HAL_PWREx_DisableVddUSB();
}
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
/* USER CODE END USB_OTG_FS_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

111
Core/Src/stm32l4xx_hal_timebase_tim.c Normal file
View File

@ -0,0 +1,111 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_hal_timebase_TIM.c
* @brief HAL time base based on the hardware TIM.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#include "stm32l4xx_hal_tim.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim16;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the TIM16 as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0;
uint32_t pFLatency;
/*Configure the TIM16 IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority ,0);
/* Enable the TIM16 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
/* Enable TIM16 clock */
__HAL_RCC_TIM16_CLK_ENABLE();
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Compute TIM16 clock */
uwTimclock = HAL_RCC_GetPCLK2Freq();
/* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
/* Initialize TIM16 */
htim16.Instance = TIM16;
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim16.Init.Period = (1000000U / 1000U) - 1U;
htim16.Init.Prescaler = uwPrescalerValue;
htim16.Init.ClockDivision = 0;
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
if(HAL_TIM_Base_Init(&htim16) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim16);
}
/* Return function status */
return HAL_ERROR;
}
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling TIM16 update interrupt.
* @param None
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable TIM16 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim16, TIM_IT_UPDATE);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling TIM16 update interrupt.
* @param None
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Enable TIM16 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim16, TIM_IT_UPDATE);
}

193
Core/Src/stm32l4xx_it.c Normal file
View File

@ -0,0 +1,193 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern UART_HandleTypeDef hlpuart1;
extern TIM_HandleTypeDef htim16;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
/**
* @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
*/
void TIM1_UP_TIM16_IRQHandler(void)
{
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
/* USER CODE END TIM1_UP_TIM16_IRQn 0 */
HAL_TIM_IRQHandler(&htim16);
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
/* USER CODE END TIM1_UP_TIM16_IRQn 1 */
}
/**
* @brief This function handles LPUART1 global interrupt.
*/
void LPUART1_IRQHandler(void)
{
/* USER CODE BEGIN LPUART1_IRQn 0 */
/* USER CODE END LPUART1_IRQn 0 */
HAL_UART_IRQHandler(&hlpuart1);
/* USER CODE BEGIN LPUART1_IRQn 1 */
/* USER CODE END LPUART1_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

155
Core/Src/syscalls.c Normal file
View File

@ -0,0 +1,155 @@
/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
return -1;
}
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
return 1;
}
int _lseek(int file, int ptr, int dir)
{
return 0;
}
int _open(char *path, int flags, ...)
{
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
return -1;
}
int _stat(char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
errno = ENOMEM;
return -1;
}

79
Core/Src/sysmem.c Normal file
View File

@ -0,0 +1,79 @@
/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
* please consult the newlib libc manual
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <errno.h>
#include <stdint.h>
/**
* Pointer to the current high watermark of the heap usage
*/
static uint8_t *__sbrk_heap_end = NULL;
/**
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
* and others from the C library
*
* @verbatim
* ############################################################################
* # .data # .bss # newlib heap # MSP stack #
* # # # # Reserved by _Min_Stack_Size #
* ############################################################################
* ^-- RAM start ^-- _end _estack, RAM end --^
* @endverbatim
*
* This implementation starts allocating at the '_end' linker symbol
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
* The implementation considers '_estack' linker symbol to be RAM end
* NOTE: If the MSP stack, at any point during execution, grows larger than the
* reserved size, please increase the '_Min_Stack_Size'.
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t *max_heap = (uint8_t *)stack_limit;
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
{
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
{
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void *)prev_heap_end;
}

332
Core/Src/system_stm32l4xx.c Normal file
View File

@ -0,0 +1,332 @@
/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
#if defined(USER_VECT_TAB_ADDRESS)
/* Configure the Vector Table location -------------------------------------*/
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
/* Get MSI Range frequency--------------------------------------------------*/
if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
{ /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange;
break;
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource)
{
case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm);
break;
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
SystemCoreClock = msirange;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

550
Core/Startup/startup_stm32l4a6zgtx.s Normal file
View File

@ -0,0 +1,550 @@
/**
******************************************************************************
* @file startup_stm32l4a6xx.s
* @author MCD Application Team
* @brief STM32L4A6xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word DFSDM1_FLT3_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word SDMMC1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word DFSDM1_FLT0_IRQHandler
.word DFSDM1_FLT1_IRQHandler
.word DFSDM1_FLT2_IRQHandler
.word COMP_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word OTG_FS_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word LPUART1_IRQHandler
.word QUADSPI_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SAI1_IRQHandler
.word SAI2_IRQHandler
.word SWPMI1_IRQHandler
.word TSC_IRQHandler
.word LCD_IRQHandler
.word AES_IRQHandler
.word HASH_RNG_IRQHandler
.word FPU_IRQHandler
.word CRS_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word DCMI_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word DMA2D_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler

20089
Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

303
Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h Normal file
View File

@ -0,0 +1,303 @@
/**
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L4xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx
* @{
*/
#ifndef __STM32L4xx_H
#define __STM32L4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32L4)
#define STM32L4
#endif /* STM32L4 */
/* Uncomment the line below according to the target STM32L4 device used in your
application
*/
#if !defined (STM32L412xx) && !defined (STM32L422xx) && \
!defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
/* #define STM32L412xx */ /*!< STM32L412xx Devices */
/* #define STM32L422xx */ /*!< STM32L422xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
/* #define STM32L4P5xx */ /*!< STM32L4Q5xx Devices */
/* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */
/* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
/* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
/* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
/* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
/* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L4_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32L412xx)
#include "stm32l412xx.h"
#elif defined(STM32L422xx)
#include "stm32l422xx.h"
#elif defined(STM32L431xx)
#include "stm32l431xx.h"
#elif defined(STM32L432xx)
#include "stm32l432xx.h"
#elif defined(STM32L433xx)
#include "stm32l433xx.h"
#elif defined(STM32L442xx)
#include "stm32l442xx.h"
#elif defined(STM32L443xx)
#include "stm32l443xx.h"
#elif defined(STM32L451xx)
#include "stm32l451xx.h"
#elif defined(STM32L452xx)
#include "stm32l452xx.h"
#elif defined(STM32L462xx)
#include "stm32l462xx.h"
#elif defined(STM32L471xx)
#include "stm32l471xx.h"
#elif defined(STM32L475xx)
#include "stm32l475xx.h"
#elif defined(STM32L476xx)
#include "stm32l476xx.h"
#elif defined(STM32L485xx)
#include "stm32l485xx.h"
#elif defined(STM32L486xx)
#include "stm32l486xx.h"
#elif defined(STM32L496xx)
#include "stm32l496xx.h"
#elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h"
#else
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32l4xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32L4xx_H */
/**
* @}
*/
/**
* @}
*/

106
Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h Normal file
View File

@ -0,0 +1,106 @@
/**
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32L4XX_H
#define __SYSTEM_STM32L4XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32L4xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32L4XX_H */
/**
* @}
*/
/**
* @}
*/

6
Drivers/CMSIS/Device/ST/STM32L4xx/LICENSE.txt Normal file
View File

@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

83
Drivers/CMSIS/Device/ST/STM32L4xx/License.md Normal file
View File

@ -0,0 +1,83 @@
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
2. Grant of Copyright License.
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
3. Grant of Patent License.
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
4. Redistribution.
You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
1.You must give any other recipients of the Work or Derivative Works a copy of this License; and
2.You must cause any modified files to carry prominent notices stating that You changed the files; and
3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
5. Submission of Contributions.
Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
6. Trademarks.
This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
7. Disclaimer of Warranty.
Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
8. Limitation of Liability.
In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability.
While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
APPENDIX:
Copyright [2019] [STMicroelectronics]
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

894
Drivers/CMSIS/Include/cmsis_armcc.h Normal file
View File

@ -0,0 +1,894 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

1444
Drivers/CMSIS/Include/cmsis_armclang.h Normal file
View File

File diff suppressed because it is too large Load Diff

1891
Drivers/CMSIS/Include/cmsis_armclang_ltm.h Normal file
View File

File diff suppressed because it is too large Load Diff

283
Drivers/CMSIS/Include/cmsis_compiler.h Normal file
View File

@ -0,0 +1,283 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

2168
Drivers/CMSIS/Include/cmsis_gcc.h Normal file
View File

File diff suppressed because it is too large Load Diff

964
Drivers/CMSIS/Include/cmsis_iccarm.h Normal file
View File

@ -0,0 +1,964 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

39
Drivers/CMSIS/Include/cmsis_version.h Normal file
View File

@ -0,0 +1,39 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

2968
Drivers/CMSIS/Include/core_armv81mml.h Normal file
View File

File diff suppressed because it is too large Load Diff

1921
Drivers/CMSIS/Include/core_armv8mbl.h Normal file
View File

File diff suppressed because it is too large Load Diff

2835
Drivers/CMSIS/Include/core_armv8mml.h Normal file
View File

File diff suppressed because it is too large Load Diff

952
Drivers/CMSIS/Include/core_cm0.h Normal file
View File

@ -0,0 +1,952 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1085
Drivers/CMSIS/Include/core_cm0plus.h Normal file
View File

File diff suppressed because it is too large Load Diff

979
Drivers/CMSIS/Include/core_cm1.h Normal file
View File

@ -0,0 +1,979 @@
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1996
Drivers/CMSIS/Include/core_cm23.h Normal file
View File

File diff suppressed because it is too large Load Diff

1937
Drivers/CMSIS/Include/core_cm3.h Normal file
View File

File diff suppressed because it is too large Load Diff

2910
Drivers/CMSIS/Include/core_cm33.h Normal file
View File

File diff suppressed because it is too large Load Diff

2910
Drivers/CMSIS/Include/core_cm35p.h Normal file
View File

File diff suppressed because it is too large Load Diff

2124
Drivers/CMSIS/Include/core_cm4.h Normal file
View File

File diff suppressed because it is too large Load Diff

2725
Drivers/CMSIS/Include/core_cm7.h Normal file
View File

File diff suppressed because it is too large Load Diff

1025
Drivers/CMSIS/Include/core_sc000.h Normal file
View File

File diff suppressed because it is too large Load Diff

1912
Drivers/CMSIS/Include/core_sc300.h Normal file
View File

File diff suppressed because it is too large Load Diff

272
Drivers/CMSIS/Include/mpu_armv7.h Normal file
View File

@ -0,0 +1,272 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

346
Drivers/CMSIS/Include/mpu_armv8.h Normal file
View File

@ -0,0 +1,346 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

70
Drivers/CMSIS/Include/tz_context.h Normal file
View File

@ -0,0 +1,70 @@
/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

201
Drivers/CMSIS/LICENSE.txt Normal file
View File

@ -0,0 +1,201 @@
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity
exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications,
including but not limited to software source code, documentation
source, and configuration files.
"Object" form shall mean any form resulting from mechanical
transformation or translation of a Source form, including but
not limited to compiled object code, generated documentation,
and conversions to other media types.
"Work" shall mean the work of authorship, whether in Source or
Object form, made available under the License, as indicated by a
copyright notice that is included in or attached to the work
(an example is provided in the Appendix below).
"Derivative Works" shall mean any work, whether in Source or Object
form, that is based on (or derived from) the Work and for which the
editorial revisions, annotations, elaborations, or other modifications
represent, as a whole, an original work of authorship. For the purposes
of this License, Derivative Works shall not include works that remain
separable from, or merely link (or bind by name) to the interfaces of,
the Work and Derivative Works thereof.
"Contribution" shall mean any work of authorship, including
the original version of the Work and any modifications or additions
to that Work or Derivative Works thereof, that is intentionally
submitted to Licensor for inclusion in the Work by the copyright owner
or by an individual or Legal Entity authorized to submit on behalf of
the copyright owner. For the purposes of this definition, "submitted"
means any form of electronic, verbal, or written communication sent
to the Licensor or its representatives, including but not limited to
communication on electronic mailing lists, source code control systems,
and issue tracking systems that are managed by, or on behalf of, the
Licensor for the purpose of discussing and improving the Work, but
excluding communication that is conspicuously marked or otherwise
designated in writing by the copyright owner as "Not a Contribution."
"Contributor" shall mean Licensor and any individual or Legal Entity
on behalf of whom a Contribution has been received by Licensor and
subsequently incorporated within the Work.
2. Grant of Copyright License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
copyright license to reproduce, prepare Derivative Works of,
publicly display, publicly perform, sublicense, and distribute the
Work and such Derivative Works in Source or Object form.
3. Grant of Patent License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
(except as stated in this section) patent license to make, have made,
use, offer to sell, sell, import, and otherwise transfer the Work,
where such license applies only to those patent claims licensable
by such Contributor that are necessarily infringed by their
Contribution(s) alone or by combination of their Contribution(s)
with the Work to which such Contribution(s) was submitted. If You
institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the Work
or a Contribution incorporated within the Work constitutes direct
or contributory patent infringement, then any patent licenses
granted to You under this License for that Work shall terminate
as of the date such litigation is filed.
4. Redistribution. You may reproduce and distribute copies of the
Work or Derivative Works thereof in any medium, with or without
modifications, and in Source or Object form, provided that You
meet the following conditions:
(a) You must give any other recipients of the Work or
Derivative Works a copy of this License; and
(b) You must cause any modified files to carry prominent notices
stating that You changed the files; and
(c) You must retain, in the Source form of any Derivative Works
that You distribute, all copyright, patent, trademark, and
attribution notices from the Source form of the Work,
excluding those notices that do not pertain to any part of
the Derivative Works; and
(d) If the Work includes a "NOTICE" text file as part of its
distribution, then any Derivative Works that You distribute must
include a readable copy of the attribution notices contained
within such NOTICE file, excluding those notices that do not
pertain to any part of the Derivative Works, in at least one
of the following places: within a NOTICE text file distributed
as part of the Derivative Works; within the Source form or
documentation, if provided along with the Derivative Works; or,
within a display generated by the Derivative Works, if and
wherever such third-party notices normally appear. The contents
of the NOTICE file are for informational purposes only and
do not modify the License. You may add Your own attribution
notices within Derivative Works that You distribute, alongside
or as an addendum to the NOTICE text from the Work, provided
that such additional attribution notices cannot be construed
as modifying the License.
You may add Your own copyright statement to Your modifications and
may provide additional or different license terms and conditions
for use, reproduction, or distribution of Your modifications, or
for any such Derivative Works as a whole, provided Your use,
reproduction, and distribution of the Work otherwise complies with
the conditions stated in this License.
5. Submission of Contributions. Unless You explicitly state otherwise,
any Contribution intentionally submitted for inclusion in the Work
by You to the Licensor shall be under the terms and conditions of
this License, without any additional terms or conditions.
Notwithstanding the above, nothing herein shall supersede or modify
the terms of any separate license agreement you may have executed
with Licensor regarding such Contributions.
6. Trademarks. This License does not grant permission to use the trade
names, trademarks, service marks, or product names of the Licensor,
except as required for reasonable and customary use in describing the
origin of the Work and reproducing the content of the NOTICE file.
7. Disclaimer of Warranty. Unless required by applicable law or
agreed to in writing, Licensor provides the Work (and each
Contributor provides its Contributions) on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied, including, without limitation, any warranties or conditions
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
PARTICULAR PURPOSE. You are solely responsible for determining the
appropriateness of using or redistributing the Work and assume any
risks associated with Your exercise of permissions under this License.
8. Limitation of Liability. In no event and under no legal theory,
whether in tort (including negligence), contract, or otherwise,
unless required by applicable law (such as deliberate and grossly
negligent acts) or agreed to in writing, shall any Contributor be
liable to You for damages, including any direct, indirect, special,
incidental, or consequential damages of any character arising as a
result of this License or out of the use or inability to use the
Work (including but not limited to damages for loss of goodwill,
work stoppage, computer failure or malfunction, or any and all
other commercial damages or losses), even if such Contributor
has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability. While redistributing
the Work or Derivative Works thereof, You may choose to offer,
and charge a fee for, acceptance of support, warranty, indemnity,
or other liability obligations and/or rights consistent with this
License. However, in accepting such obligations, You may act only
on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason
of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "{}"
replaced with your own identifying information. (Don't include
the brackets!) The text should be enclosed in the appropriate
comment syntax for the file format. We also recommend that a
file or class name and description of purpose be included on the
same "printed page" as the copyright notice for easier
identification within third-party archives.
Copyright {yyyy} {name of copyright owner}
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

3986
Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Normal file
View File

File diff suppressed because it is too large Load Diff

726
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h Normal file
View File

@ -0,0 +1,726 @@
/**
******************************************************************************
* @file stm32l4xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_H
#define STM32L4xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_conf.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0U
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4P5xx || STM32L4Q5xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2)
#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)
#else
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @}
*/
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
#if defined(SYSCFG_SWPR_PAGE31)
#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
#endif /* SYSCFG_SWPR_PAGE31 */
/**
* @}
*/
#if defined(SYSCFG_SWPR2_PAGE63)
/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
/**
* @}
*/
#endif /* SYSCFG_SWPR2_PAGE63 */
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSCFG_flags_definition Flags
* @{
*/
#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#endif
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#endif
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#endif
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief Main Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4P5xx || STM32L4Q5xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/** @brief OCTOSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))
#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))
#else
/** @brief QUADSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @brief Return the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg @ref SYSCFG_BOOT_MAINFLASH
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
@if STM32L486xx
* @arg @ref SYSCFG_BOOT_FMC
@endif
* @arg @ref SYSCFG_BOOT_SRAM
@if STM32L422xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L443xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L462xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L486xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief SRAM2 page 0 to 31 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
}while(0)
#if defined(SYSCFG_SWPR2_PAGE63)
/** @brief SRAM2 page 32 to 63 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
}while(0)
#endif /* SYSCFG_SWPR2_PAGE63 */
/** @brief SRAM2 page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
*/
#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
SYSCFG->SKR = 0x53;\
}while(0)
/** @brief SRAM2 erase
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
*/
#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break SRAM2 parity lock.
* Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked by system reset.
*/
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
/** @brief Check SYSCFG flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#elif defined(SYSCFG_FASTMODEPLUS_PB8)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
#elif defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#else
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SYSCFG Control functions ****************************************************/
void HAL_SYSCFG_SRAM2Erase(void);
void HAL_SYSCFG_EnableMemorySwappingBank(void);
void HAL_SYSCFG_DisableMemorySwappingBank(void);
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_H */

420
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h Normal file
View File

@ -0,0 +1,420 @@
/**
******************************************************************************
* @file stm32l4xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CORTEX_H
#define STM32L4xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2) || \
((TYPE) == MPU_TEX_LEVEL4))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_CORTEX_H */

209
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h Normal file
View File

@ -0,0 +1,209 @@
/**
******************************************************************************
* @file stm32l4xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DEF_H
#define STM32L4xx_HAL_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5 */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DEF_H */

861
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h Normal file
View File

@ -0,0 +1,861 @@
/**
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_H
#define STM32L4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Request; /*!< Specifies the request selected for the specified channel.
This parameter can be a value of @ref DMA_request */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
#if defined(DMAMUX1)
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
#endif /* DMAMUX1 */
}DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
/**
* @}
*/
/** @defgroup DMA_request DMA request
* @{
*/
#if !defined (DMAMUX1)
#define DMA_REQUEST_0 0U
#define DMA_REQUEST_1 1U
#define DMA_REQUEST_2 2U
#define DMA_REQUEST_3 3U
#define DMA_REQUEST_4 4U
#define DMA_REQUEST_5 5U
#define DMA_REQUEST_6 6U
#define DMA_REQUEST_7 7U
#endif
#if defined(DMAMUX1)
#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */
#define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */
#define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */
#define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */
#define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */
#define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */
#define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */
#define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */
#define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */
#define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */
#define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */
#define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */
#define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */
#define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */
#define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */
#define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */
#define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */
#define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */
#define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */
#define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */
#define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */
#define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */
#define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */
#define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */
#define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */
#define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */
#define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */
#define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */
#define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */
#define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */
#define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */
#define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */
#define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */
#define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */
#define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */
#define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */
#define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */
#define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */
#define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */
#define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */
#define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */
#define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */
#define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */
#define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */
#define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */
#define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */
#define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */
#define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */
#define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */
#define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */
#define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */
#define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */
#define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */
#define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */
#define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */
#define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */
#define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */
#define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */
#define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */
#define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */
#define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */
#define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */
#define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */
#define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */
#define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */
#define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */
#define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */
#define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */
#define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */
#define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */
#define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */
#define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */
#define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */
#define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */
#define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */
#define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */
#define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */
#define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */
#define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */
#define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */
#else
#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */
#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */
#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */
#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */
#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */
#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */
#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */
#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */
#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */
#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */
#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */
#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */
#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */
#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */
#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */
#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */
#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */
#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */
#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */
#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */
#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */
#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */
#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */
#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */
#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */
#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */
#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */
#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */
#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */
#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */
#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */
#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */
#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */
#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */
#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */
#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */
#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */
#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */
#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */
#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */
#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */
#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */
#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */
#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */
#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */
#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */
#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */
#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */
#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */
#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */
#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */
#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */
#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */
#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */
#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */
#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */
#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */
#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */
#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */
#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */
#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */
#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */
#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */
#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */
#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */
#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */
#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */
#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */
#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */
#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */
#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */
#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */
#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */
#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */
#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */
#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */
#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */
#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */
#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */
#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */
#endif /* STM32L4P5xx || STM32L4Q5xx */
#endif /* DMAMUX1 */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 DMA_ISR_GIF1
#define DMA_FLAG_TC1 DMA_ISR_TCIF1
#define DMA_FLAG_HT1 DMA_ISR_HTIF1
#define DMA_FLAG_TE1 DMA_ISR_TEIF1
#define DMA_FLAG_GL2 DMA_ISR_GIF2
#define DMA_FLAG_TC2 DMA_ISR_TCIF2
#define DMA_FLAG_HT2 DMA_ISR_HTIF2
#define DMA_FLAG_TE2 DMA_ISR_TEIF2
#define DMA_FLAG_GL3 DMA_ISR_GIF3
#define DMA_FLAG_TC3 DMA_ISR_TCIF3
#define DMA_FLAG_HT3 DMA_ISR_HTIF3
#define DMA_FLAG_TE3 DMA_ISR_TEIF3
#define DMA_FLAG_GL4 DMA_ISR_GIF4
#define DMA_FLAG_TC4 DMA_ISR_TCIF4
#define DMA_FLAG_HT4 DMA_ISR_HTIF4
#define DMA_FLAG_TE4 DMA_ISR_TEIF4
#define DMA_FLAG_GL5 DMA_ISR_GIF5
#define DMA_FLAG_TC5 DMA_ISR_TCIF5
#define DMA_FLAG_HT5 DMA_ISR_HTIF5
#define DMA_FLAG_TE5 DMA_ISR_TEIF5
#define DMA_FLAG_GL6 DMA_ISR_GIF6
#define DMA_FLAG_TC6 DMA_ISR_TCIF6
#define DMA_FLAG_HT6 DMA_ISR_HTIF6
#define DMA_FLAG_TE6 DMA_ISR_TEIF6
#define DMA_FLAG_GL7 DMA_ISR_GIF7
#define DMA_FLAG_TC7 DMA_ISR_TCIF7
#define DMA_FLAG_HT7 DMA_ISR_HTIF7
#define DMA_FLAG_TE7 DMA_ISR_TEIF7
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
#if defined(DMAMUX1)
/* Include DMA HAL Extension module */
#include "stm32l4xx_hal_dma_ex.h"
#endif /* DMAMUX1 */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#if !defined (DMAMUX1)
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
((REQUEST) == DMA_REQUEST_1) || \
((REQUEST) == DMA_REQUEST_2) || \
((REQUEST) == DMA_REQUEST_3) || \
((REQUEST) == DMA_REQUEST_4) || \
((REQUEST) == DMA_REQUEST_5) || \
((REQUEST) == DMA_REQUEST_6) || \
((REQUEST) == DMA_REQUEST_7))
#endif
#if defined(DMAMUX1)
#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
#endif /* DMAMUX1 */
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DMA_H */

284
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h Normal file
View File

@ -0,0 +1,284 @@
/**
******************************************************************************
* @file stm32l4xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_EX_H
#define STM32L4xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(DMAMUX1)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @{
*/
/**
* @brief HAL DMA Synchro definition
*/
/**
* @brief HAL DMAMUX Synchronization configuration structure definition
*/
typedef struct
{
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxSyncConfigTypeDef;
/**
* @brief HAL DMAMUX request generator parameters structure definition
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
* @{
*/
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
* @{
*/
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
* @{
*/
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{
*/
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup DMAEx_Exported_Functions_Group1
* @{
*/
/* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
/* -------------------------------------------------------------------------- */
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx private macros
* @{
*/
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMAMUX1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DMA_H */

858
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h Normal file
View File

@ -0,0 +1,858 @@
/**
******************************************************************************
* @file stm32l4xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_EXTI_H
#define STM32L4xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#if defined(STM32L412xx) || defined(STM32L422xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L412xx || STM32L422xx */
#if defined(STM32L431xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L431xx */
#if defined(STM32L432xx) || defined(STM32L442xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L432xx || STM32L442xx */
#if defined(STM32L433xx) || defined(STM32L443xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L433xx || STM32L443xx */
#if defined(STM32L451xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L451xx */
#if defined(STM32L452xx) || defined(STM32L462xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L452xx || STM32L462xx */
#if defined(STM32L471xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L471xx */
#if defined(STM32L475xx) || defined(STM32L485xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L475xx || STM32L485xx */
#if defined(STM32L476xx) || defined(STM32L486xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L476xx || STM32L486xx */
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L496xx || STM32L4A6xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOF 0x00000005u
#define EXTI_GPIOG 0x00000006u
#define EXTI_GPIOH 0x00000007u
#define EXTI_GPIOI 0x00000008u
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Event presence definition
*/
#define EXTI_EVENT_PRESENCE_SHIFT 28u
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 41u
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined(STM32L412xx) || defined(STM32L422xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L412xx || STM32L422xx */
#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
#if defined(STM32L432xx) || defined(STM32L442xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L432xx || STM32L442xx */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#endif /* STM32L496xx || STM32L4A6xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_EXTI_H */

1028
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h Normal file
View File

File diff suppressed because it is too large Load Diff

125
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h Normal file
View File

@ -0,0 +1,125 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_FLASH_EX_H
#define STM32L4xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#if defined (FLASH_CFGR_LVEN)
/** @addtogroup FLASHEx_Exported_Constants
* @{
*/
/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration
* @{
*/
#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */
#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */
/**
* @}
*/
/**
* @}
*/
#endif /* FLASH_CFGR_LVEN */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/**
* @}
*/
#if defined (FLASH_CFGR_LVEN)
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);
/**
* @}
*/
#endif /* FLASH_CFGR_LVEN */
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
void FLASH_FlushCaches(void);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/**
@cond 0
*/
#if defined (FLASH_CFGR_LVEN)
#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED))
#endif /* FLASH_CFGR_LVEN */
/**
@endcond
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_FLASH_EX_H */

74
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h Normal file
View File

@ -0,0 +1,74 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_FLASH_RAMFUNC_H
#define STM32L4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ************************************************/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_FLASH_RAMFUNC_H */

323
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h Normal file
View File

@ -0,0 +1,323 @@
/**
******************************************************************************
* @file stm32l4xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_GPIO_H
#define STM32L4xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_ANALOG_ADC_CONTROL (MODE_ANALOG | 0x8uL) /*!< Analog Mode for ADC conversion (0x0000000Bu)*/
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0u
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4u
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16u
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20u
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG) ||\
((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32l4xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_GPIO_H */

1059
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h Normal file
View File

File diff suppressed because it is too large Load Diff

839
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h Normal file
View File

@ -0,0 +1,839 @@
/**
******************************************************************************
* @file stm32l4xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_I2C_H
#define STM32L4xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32l4xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32l4xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_I2C_H */

184
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h Normal file
View File

@ -0,0 +1,184 @@
/**
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_I2C_EX_H
#define STM32L4xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#else
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
#endif /* SYSCFG_CFGR1_I2C2_FMP */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_I2C_EX_H */

1058
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h Normal file
View File

File diff suppressed because it is too large Load Diff

92
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h Normal file
View File

@ -0,0 +1,92 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.h
* @author MCD Application Team
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_PCD_EX_H
#define STM32L4xx_HAL_PCD_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
#if defined (USB_OTG_FS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
#endif /* defined (USB) */
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32L4xx_HAL_PCD_EX_H */

411
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h Normal file
View File

@ -0,0 +1,411 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_PWR_H
#define STM32L4xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
/**
* @}
*/
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
* @{
*/
#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief Check whether or not a specific PWR flag is set.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
* entered StandBy mode.
* @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates
* that external switch can be closed to connect to the external SMPS, when the Range 2
* of internal regulator is ready.
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
* the internal wakeup line.
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
* low-power regulator is ready.
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
* regulator is ready in main mode or is in low-power mode.
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
* in the selected voltage range or is still changing to the required voltage level.
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
* below or above the selected PVD threshold.
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
* is below or above PVM1 threshold (applicable when USB feature is supported).
@if STM32L486xx
* @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
* is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
@endif
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
* is below or above PVM3 threshold.
* @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
* is below or above PVM4 threshold.
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/** @brief Clear a specific PWR flag.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
* @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
* entered Standby mode.
* @retval None
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
(PWR->SCR = (__FLAG__)) :\
(PWR->SCR = (1U << ((__FLAG__) & 31U))) )
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @brief Check whether or not the PVD EXTI interrupt flag is set.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
/**
* @brief Clear the PVD EXTI interrupt flag.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32l4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_PWR_H */

929
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h Normal file
View File

@ -0,0 +1,929 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_PWR_EX_H
#define STM32L4xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
/**
* @brief PWR PVM configuration structure definition
*/
typedef struct
{
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
This parameter can be a value of @ref PWREx_PVM_Type.
@arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
@if STM32L486xx
@arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
@endif
@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
@arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_PVM_Mode. */
}PWR_PVMTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
* @{
*/
#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
/**
* @}
*/
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
* @{
*/
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
/**
* @}
*/
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
#endif /* PWR_CR2_PVME2 */
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
#define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
/**
* @}
*/
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
* @{
*/
#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
* @{
*/
#if defined(PWR_CR5_R1MODE)
#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
#endif
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
* @{
*/
#define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
/**
* @}
*/
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
* @{
*/
#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
/**
* @}
*/
/** @defgroup PWREx_GPIO GPIO port
* @{
*/
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
#if defined(GPIOD_BASE)
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
#endif
#if defined(GPIOE_BASE)
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
#endif
#if defined(GPIOF_BASE)
#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
#endif
#if defined(GPIOG_BASE)
#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
#endif
#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */
#if defined(GPIOI_BASE)
#define PWR_GPIO_I 0x00000008U /*!< GPIO port I */
#endif
/**
* @}
*/
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_Flag PWR Status Flags
* Elements values convention: 0000 0000 0XXY YYYYb
* - Y YYYY : Flag position in the XX register (5 bits)
* - XX : Status register (2 bits)
* - 01: SR1 register
* - 10: SR2 register
* The only exception is PWR_FLAG_WU, encompassing all
* wake-up flags and set to PWR_SR1_WUF.
* @{
*/
#define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
#define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
#define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
#define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
#define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
#define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
#if defined(PWR_SR1_EXT_SMPS_RDY)
#define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */
#endif /* PWR_SR1_EXT_SMPS_RDY */
#define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
#define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
#define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
#define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
#define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
#endif /* PWR_CR2_PVME2 */
#define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
#define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
/**
* @}
*/
/** @defgroup PWREx_SRAM2_Retention PWR SRAM2 Retention in Standby mode
* @{
*/
#define PWR_NO_SRAM2_RETENTION ((uint32_t)0x00000000) /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost) */
#if defined(PWR_CR3_RRS_1)
#define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */
#define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode */
#else
#define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */
#endif /* PWR_CR3_RRS_1 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
#if defined(PWR_CR2_PVME1)
/**
* @brief Enable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Disable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
/**
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
* @retval EXTI PVM1 Line Status.
*/
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
/**
* @brief Clear the PVM1 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
/**
* @brief Enable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Disable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
/**
* @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
* @retval EXTI PVM2 Line Status.
*/
#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
/**
* @brief Clear the PVM2 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
#endif /* PWR_CR2_PVME2 */
/**
* @brief Enable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Disable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
/**
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
* @retval EXTI PVM3 Line Status.
*/
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
/**
* @brief Clear the PVM3 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Disable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
/**
* @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
* @retval EXTI PVM4 Line Status.
*/
#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
/**
* @brief Clear the PVM4 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Configure the main internal regulator output voltage.
* @param __REGULATOR__ specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
* typical output voltage at 1.2 V,
* system frequency up to 80 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
* typical output voltage at 1.0 V,
* system frequency up to 26 MHz.
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
UNUSED(tmpreg); \
} while(0)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW))
#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#elif defined (STM32L471xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#endif
#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#endif
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
#if defined(PWR_CR5_R1MODE)
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#else
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#endif
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#if defined (STM32L412xx) || defined (STM32L422xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L432xx) || defined (STM32L442xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H) ||\
((GPIO) == PWR_GPIO_I))
#endif
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
((SRAM2) == PWR_FULL_SRAM2_RETENTION) ||\
((SRAM2) == PWR_4KBYTES_SRAM2_RETENTION))
#else
#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
((SRAM2) == PWR_FULL_SRAM2_RETENTION))
#endif
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
void HAL_PWREx_DisableBatteryCharging(void);
#if defined(PWR_CR2_USV)
void HAL_PWREx_EnableVddUSB(void);
void HAL_PWREx_DisableVddUSB(void);
#endif /* PWR_CR2_USV */
#if defined(PWR_CR2_IOSV)
void HAL_PWREx_EnableVddIO2(void);
void HAL_PWREx_DisableVddIO2(void);
#endif /* PWR_CR2_IOSV */
void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
void HAL_PWREx_EnableSRAM2ContentRetention(void);
void HAL_PWREx_DisableSRAM2ContentRetention(void);
HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size);
#if defined(PWR_CR1_RRSTP)
void HAL_PWREx_EnableSRAM3ContentRetention(void);
void HAL_PWREx_DisableSRAM3ContentRetention(void);
#endif /* PWR_CR1_RRSTP */
#if defined(PWR_CR3_DSIPDEN)
void HAL_PWREx_EnableDSIPinsPDActivation(void);
void HAL_PWREx_DisableDSIPinsPDActivation(void);
#endif /* PWR_CR3_DSIPDEN */
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_EnablePVM2(void);
void HAL_PWREx_DisablePVM2(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void);
void HAL_PWREx_EnablePVM4(void);
void HAL_PWREx_DisablePVM4(void);
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
#if defined(PWR_CR3_ENULP)
void HAL_PWREx_EnableBORPVD_ULP(void);
void HAL_PWREx_DisableBORPVD_ULP(void);
#endif /* PWR_CR3_ENULP */
#if defined(PWR_CR4_EXT_SMPS_ON)
void HAL_PWREx_EnableExtSMPS_0V95(void);
void HAL_PWREx_DisableExtSMPS_0V95(void);
#endif /* PWR_CR4_EXT_SMPS_ON */
/* Low Power modes configuration functions ************************************/
void HAL_PWREx_EnableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_PVM1Callback(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_PVM2Callback(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_PVM3Callback(void);
void HAL_PWREx_PVM4Callback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_PWR_EX_H */

4883
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h Normal file
View File

File diff suppressed because it is too large Load Diff

3045
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h Normal file
View File

File diff suppressed because it is too large Load Diff

2390
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h Normal file
View File

File diff suppressed because it is too large Load Diff

439
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h Normal file
View File

@ -0,0 +1,439 @@
/**
******************************************************************************
* @file stm32l4xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_TIM_EX_H
#define STM32L4xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct
{
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#if defined (ADC3)
#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#endif /* ADC3 */
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#endif /* COMP2 */
#if defined (USB_OTG_FS)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */
#else
#if defined(STM32L471xx)
#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */
#else
#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
#endif /* STM32L471xx */
#endif /* USB_OTG_FS */
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */
#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#endif /* COMP2 */
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */
#if defined(COMP2)
#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#endif /* COMP2 */
#if defined (TIM3)
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */
#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
#endif /* TIM3 */
#if defined (TIM8)
#if defined(ADC2) && defined(ADC3)
#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#endif /* ADC2 && ADC3 */
#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */
#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */
#endif /* TIM8 */
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */
#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */
#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */
#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#if defined (TIM3)
#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM3 */
#if defined (TIM4)
#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* TIM4 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */
#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */
#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
#if defined (TIM16_OR1_TI1_RMP_2)
#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */
#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
#endif /* TIM16_OR1_TI1_RMP_2 */
#if defined (TIM17)
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */
#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */
#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
#endif /* TIM17 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#if defined (DFSDM1_Channel0)
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#endif /* DFSDM1_Channel0 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined (DFSDM1_Channel0)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#endif /* DFSDM1_Channel0 */
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_TIM_EX_H */

1788
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h Normal file
View File

File diff suppressed because it is too large Load Diff

743
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h Normal file
View File

@ -0,0 +1,743 @@
/**
******************************************************************************
* @file stm32l4xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_UART_EX_H
#define STM32L4xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
#if defined(USART_CR1_FIFOEN)
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
#endif /* USART_CR1_FIFOEN */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
#if defined(USART_CR1_FIFOEN)
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
#endif /* USART_CR1_FIFOEN */
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
#if defined(USART_CR3_UCESM)
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
#endif /* USART_CR3_UCESM */
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
#if defined(USART_CR1_FIFOEN)
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
#endif /* USART_CR1_FIFOEN */
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \
|| defined (STM32L496xx) || defined (STM32L4A6xx) \
|| defined (STM32L4P5xx) || defined (STM32L4Q5xx) \
|| defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined (STM32L412xx) || defined (STM32L422xx) \
|| defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined (STM32L432xx) || defined (STM32L442xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx ||
* STM32L496xx || STM32L4A6xx ||
* STM32L4P5xx || STM32L4Q5xx ||
* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx
*/
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
#if defined(USART_CR1_FIFOEN)
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
#endif /* USART_CR1_FIFOEN */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_UART_EX_H */

692
Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h Normal file
View File

@ -0,0 +1,692 @@
/**
******************************************************************************
* @file stm32l4xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_USB_H
#define STM32L4xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
#if defined (USB_OTG_FS)
typedef enum
{
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
} USB_ModeTypeDef;
/**
* @brief URB States definition
*/
typedef enum
{
URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
} USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
typedef enum
{
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
/**
* @brief USB Instance Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_size; /*!< requested transfer size */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef;
typedef struct
{
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_num; /*!< Endpoint number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host Channel speed.
This parameter can be any value of @ref HCD_Device_Speed:
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t data_pid; /*!< Initial data PID.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
uint8_t toggle_in; /*!< IN transfer current toggle flag.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t toggle_out; /*!< OUT transfer current toggle flag
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count. */
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
#endif /* defined (USB) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
#if defined (USB_OTG_FS)
/** @defgroup USB_OTG_CORE VERSION ID
* @{
*/
#define USB_OTG_CORE_ID_300A 0x4F54300AU
#define USB_OTG_CORE_ID_310A 0x4F54310AU
/**
* @}
*/
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
*/
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
*/
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3U
/**
* @}
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ USB_OTG_HOST_CHANNEL_BASE\
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
#endif /* defined (USB) */
#if defined (USB_OTG_FS)
#define EP_ADDR_MSK 0xFU
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define EP_ADDR_MSK 0x7U
#endif /* defined (USB) */
#ifndef USB_EP_RX_STRX
#define USB_EP_RX_STRX (0x3U << 12)
#endif /* USB_EP_RX_STRX */
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* defined (USB_OTG_FS) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
#endif /* defined (USB) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32L4xx_LL_USB_H */

6
Drivers/STM32L4xx_HAL_Driver/LICENSE.txt Normal file
View File

@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

3
Drivers/STM32L4xx_HAL_Driver/License.md Normal file
View File

@ -0,0 +1,3 @@
# Copyright (c) 2017 STMicroelectronics
This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).

764
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c Normal file
View File

@ -0,0 +1,764 @@
/**
******************************************************************************
* @file stm32l4xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32L4xx HAL Driver version number
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
|(STM32L4XX_HAL_VERSION_SUB2 << 8U)\
|(STM32L4XX_HAL_VERSION_RC))
#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
#endif /* VREFBUF */
/* ------------ SYSCFG registers bit address in the alias region ------------ */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- MEMRMP Register ---*/
/* Alias word address of FB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define FB_MODE_BitNumber 8U
#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U))
/* --- SCSR Register ---*/
/* Alias word address of SRAM2ER bit */
#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U)
#define BRER_BitNumber 0U
#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the Flash interface, the NVIC allocation and initial time base
clock configuration.
(+) De-initialize common part of the HAL.
(+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief Configure the Flash prefetch, the Instruction and Data caches,
* the time base source, NVIC and any required global low level hardware
* by calling the HAL_MspInit() callback function to be optionally defined in user file
* stm32l4xx_hal_msp.c.
*
* @note HAL_Init() function is called at the beginning of program after reset and before
* the clock configuration.
*
* @note In the default implementation the System Timer (Systick) is used as source of time base.
* The Systick configuration is based on MSI clock, as MSI is the clock
* used after a system Reset and the NVIC configuration is set to Priority group 4.
* Once done, time base tick starts incrementing: the tick variable counter is incremented
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Configure Flash prefetch, Instruction cache, Data cache */
/* Default configuration at reset is: */
/* - Prefetch disabled */
/* - Instruction cache enabled */
/* - Data cache enabled */
#if (INSTRUCTION_CACHE_ENABLE == 0)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE == 0)
__HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Init the low level hardware */
HAL_MspInit();
}
/* Return function status */
return status;
}
/**
* @brief De-initialize common part of the HAL and stop the source of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
__HAL_RCC_AHB2_FORCE_RESET();
__HAL_RCC_AHB2_RELEASE_RESET();
__HAL_RCC_AHB3_FORCE_RESET();
__HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
}
/**
* @brief Provide a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @param Freq tick frequency
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)uwTickFreq;
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Return the HAL revision.
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return STM32L4XX_HAL_VERSION;
}
/**
* @brief Return the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
}
/**
* @brief Return the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
* @brief HAL Debug functions
*
@verbatim
===============================================================================
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
* @brief HAL SYSCFG configuration functions
*
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a hardware SRAM2 erase operation
(+) Enable/Disable the Internal FLASH Bank Swapping
(+) Configure the Voltage reference buffer
(+) Enable/Disable the Voltage reference buffer
(+) Enable/Disable the I/O analog switch voltage booster
@endverbatim
* @{
*/
/**
* @brief Start a hardware SRAM2 erase operation.
* @note As long as SRAM2 is not erased the SRAM2ER bit will be set.
* This bit is automatically reset at the end of the SRAM2 erase operation.
* @retval None
*/
void HAL_SYSCFG_SRAM2Erase(void)
{
/* unlock the write protection of the SRAM2ER bit */
SYSCFG->SKR = 0xCA;
SYSCFG->SKR = 0x53;
/* Starts a hardware SRAM2 erase operation*/
*(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL;
}
/**
* @brief Enable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32L4xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
*
* @retval None
*/
void HAL_SYSCFG_EnableMemorySwappingBank(void)
{
*(__IO uint32_t *)FB_MODE_BB = 0x00000001UL;
}
/**
* @brief Disable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32L4xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
* and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
*
* @retval None
*/
void HAL_SYSCFG_DisableMemorySwappingBank(void)
{
*(__IO uint32_t *)FB_MODE_BB = 0x00000000UL;
}
#if defined(VREFBUF)
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
}
/**
* @brief Configure the internal voltage reference buffer high impedance mode.
* @param Mode specifies the high impedance mode
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
}
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @retval None
*/
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
}
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
{
if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
*
* @retval None
*/
void HAL_SYSCFG_DisableVREFBUF(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
#endif /* VREFBUF */
/**
* @brief Enable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

517
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c Normal file
View File

@ -0,0 +1,517 @@
/**
******************************************************************************
* @file stm32l4xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32l4xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
==========================================================================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
#if (__MPU_PRESENT == 1)
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1174
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c Normal file
View File

File diff suppressed because it is too large Load Diff

307
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c Normal file
View File

@ -0,0 +1,307 @@
/**
******************************************************************************
* @file stm32l4xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(DMAMUX1)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
@endverbatim
* @{
*/
/**
* @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/*DMA State not Ready*/
return HAL_ERROR;
}
}
/**
* @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
* contains the request generator parameters.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Disable the request generator*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handles DMAMUX interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval None
*/
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if(hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* DMAMUX1 */

632
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c Normal file
View File

@ -0,0 +1,632 @@
/**
******************************************************************************
* @file stm32l4xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between MCU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between MCU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
/* Configure event mode : read current mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending register address */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

764
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c Normal file
View File

@ -0,0 +1,764 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) Prefetch on I-Code
(+) 32 cache lines of 4*64 bits on I-Code
(+) 8 cache lines of 4*64 bits on D-Code
(+) Error code correction (ECC) : Data in flash are 72-bits word
(8 bits added per double word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32L4xx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: double word and fast program (full row programming)
(++) There Two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions :
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the Instruction cache and the Data cache
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the Flash power-down during low-power run and sleep modes
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64
#else
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
#endif
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
.ErrorCode = HAL_FLASH_ERROR_NONE, \
.ProcedureOnGoing = FLASH_PROC_NONE, \
.Address = 0U, \
.Bank = FLASH_BANK_1, \
.Page = 0U, \
.NbPagesToErase = 0U, \
.CacheToReactivate = FLASH_CACHE_DISABLED};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program double word or fast program of a row at a specified address.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status;
uint32_t prog_bit = 0;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
prog_bit = FLASH_CR_PG;
}
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
/* If it is the last row, the bit will be cleared at the end of the operation */
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
prog_bit = FLASH_CR_FSTPG;
}
}
else
{
/* Nothing to do */
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG or FSTPG Bit */
if (prog_bit != 0U)
{
CLEAR_BIT(FLASH->CR, prog_bit);
}
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches();
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Program double word or fast program of a row at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
/* Set internal variables used by the IRQ handler */
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
}
pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
}
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
}
else
{
/* Nothing to do */
}
return status;
}
/**
* @brief Handle FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t tmp_page;
uint32_t error;
FLASH_ProcedureTypeDef procedure;
/* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
#endif
/* Disable the FSTPG Bit only if it is the last row programmed */
if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
{
CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
}
/* Check FLASH operation error flags */
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if (error !=0U)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH error interrupt user callback */
procedure = pFlash.ProcedureOnGoing;
if(procedure == FLASH_PROC_PAGE_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Page);
}
else if(procedure == FLASH_PROC_MASS_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Bank);
}
else if((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
HAL_FLASH_OperationErrorCallback(pFlash.Address);
}
else
{
HAL_FLASH_OperationErrorCallback(0U);
}
/*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase*/
if(pFlash.NbPagesToErase != 0U)
{
/* Indicate user which page has been erased*/
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
/* Increment page number */
pFlash.Page++;
tmp_page = pFlash.Page;
FLASH_PageErase(tmp_page, pFlash.Bank);
}
else
{
/* No more pages to Erase */
/* Reset Address and stop Erase pages procedure */
pFlash.Page = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
}
}
else
{
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
procedure = pFlash.ProcedureOnGoing;
if(procedure == FLASH_PROC_MASS_ERASE)
{
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
else if((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
else
{
/* Nothing to do */
}
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Disable End of Operation and Error interrupts */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page number which returned an error
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Lock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
return HAL_OK;
}
/**
* @brief Launch the option byte loading.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
* @arg HAL_FLASH_ERROR_NONE: No error set
* @arg HAL_FLASH_ERROR_OP: FLASH Operation error
* @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
* @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
* @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
* @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
* @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
* @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
* @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
uint32_t error;
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if(Timeout != HAL_MAX_DELAY)
{
if((HAL_GetTick() - tickstart) >= Timeout)
{
return HAL_TIMEOUT;
}
}
}
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if(error != 0u)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* If there is an error flag set */
return HAL_OK;
}
/**
* @brief Program double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);
}
/**
* @brief Fast program a row double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
{
uint32_t primask_bit;
uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
__IO uint32_t *dest_addr = (__IO uint32_t*)Address;
__IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set FSTPG bit */
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
/* Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the double word of the row */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Re-enable the interrupts */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1316
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

251
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c Normal file
View File

@ -0,0 +1,251 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
* + FLASH HalfPage Programming
* + FLASH Power Down in Run mode
*
* @verbatim
==============================================================================
##### Flash RAM functions #####
==============================================================================
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM.
@endverbatim
* @{
*/
/**
* @brief Enable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
{
/* Disable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_DISABLE();
return HAL_OK;
}
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/**
* @brief Program the FLASH DBANK User Option Byte.
*
* @note To configure the user option bytes, the option lock bit OPTLOCK must
* be cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To modify the DBANK option byte, no PCROP region should be defined.
* To deactivate PCROP, user should perform RDP changing
*
* @param DBankConfig The FLASH DBANK User Option Byte value.
* This parameter can be one of the following values:
* @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
* @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
*
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
{
uint32_t count, reg;
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check if the PCROP is disabled */
reg = FLASH->PCROP1SR;
if (reg > FLASH->PCROP1ER)
{
reg = FLASH->PCROP2SR;
if (reg > FLASH->PCROP2ER)
{
/* Disable Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_DISABLE();
if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
{
/* Disable Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
/* Flush Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
}
if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable Flash data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
/* Flush Flash data cache */
__HAL_FLASH_DATA_CACHE_RESET();
}
/* Disable WRP zone 1 of 1st bank if needed */
reg = FLASH->WRP1AR;
if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
{
MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
}
/* Disable WRP zone 2 of 1st bank if needed */
reg = FLASH->WRP1BR;
if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
{
MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
}
/* Disable WRP zone 1 of 2nd bank if needed */
reg = FLASH->WRP2AR;
if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
{
MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
}
/* Disable WRP zone 2 of 2nd bank if needed */
reg = FLASH->WRP2BR;
if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
{
MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
}
/* Modify the DBANK user option byte */
MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
/* Set OPTSTRT Bit */
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Wait for last operation to be completed */
/* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
do
{
if (count == 0U)
{
break;
}
count--;
} while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
/* If the option byte program operation is completed, disable the OPTSTRT Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

551
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c Normal file
View File

@ -0,0 +1,551 @@
/**
******************************************************************************
* @file stm32l4xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 39 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
#define GPIO_NUMBER (16u)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00u;
uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
temp |= (GPIO_Init->Speed << (position * 2u));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
temp &= ~(GPIO_ASCR_ASC0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
GPIOx->ASCR = temp;
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
temp &= ~(0xFu << ((position & 0x07u) * 4u));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
GPIOx->AFR[position >> 3u] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2u];
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2u] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
{
temp |= iocurrent;
}
EXTI->EMR1 = temp;
temp = EXTI->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
{
temp |= iocurrent;
}
EXTI->IMR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00u;
uint32_t iocurrent;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00u)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1uL << position);
if (iocurrent != 0x00u)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2u];
tmp &= (0x0FuL << (4u * (position & 0x03u)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->FTSR1 &= ~(iocurrent);
EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FuL << (4u * (position & 0x03u));
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* Deactivate the Control bit of Analog mode for the current IO */
GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
}
position++;
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
*
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the pin to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* Read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

7162
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c Normal file
View File

File diff suppressed because it is too large Load Diff

368
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c Normal file
View File

@ -0,0 +1,368 @@
/**
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32L4xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

2943
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c Normal file
View File

File diff suppressed because it is too large Load Diff

561
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c Normal file
View File

@ -0,0 +1,561 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB) || defined (USB_OTG_FS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait for Min DCD Timeout */
HAL_Delay(300U);
/* Check Detect flag */
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
/* Check for the Timeout, else start USB Device */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
/* Power Down USB transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
hpcd->battery_charging_active = 0U;
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/**
* @brief Configure PMA for EP
* @param hpcd Device instance
* @param ep_addr endpoint address
* @param ep_kind endpoint Kind
* USB_SNG_BUF: Single Buffer used
* USB_DBL_BUF: Double Buffer used
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
* this parameter is 16-bit value providing the address
* in PMA allocated to endpoint.
* In case of double buffer endpoint this parameter
* is a 32-bit value providing the endpoint buffer 0 address
* in the LSB part of 32-bit value and endpoint buffer 1 address
* in the MSB part of 32-bit value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
{
/* Single Buffer */
ep->doublebuffer = 0U;
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 1U;
/* Enable BCD feature */
USBx->BCDR |= USB_BCDR_BCDEN;
/* Enable DCD : Data Contact Detect */
USBx->BCDR &= ~(USB_BCDR_PDEN);
USBx->BCDR &= ~(USB_BCDR_SDEN);
USBx->BCDR |= USB_BCDR_DCDEN;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 0U;
/* Disable BCD feature */
USBx->BCDR &= ~(USB_BCDR_BCDEN);
return HAL_OK;
}
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Wait for Min DCD Timeout */
HAL_Delay(300U);
/* Data Pin Contact ? Check Detect flag */
if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->BCDR &= ~(USB_BCDR_DCDEN);
HAL_Delay(50U);
USBx->BCDR |= (USB_BCDR_PDEN);
HAL_Delay(50U);
/* If Charger detect ? */
if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
{
/* Start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->BCDR &= ~(USB_BCDR_PDEN);
HAL_Delay(50U);
USBx->BCDR |= (USB_BCDR_SDEN);
HAL_Delay(50U);
/* If CDP ? */
if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
{
/* Dedicated Downstream Port DCP */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Charging Downstream Port CDP */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else /* NO */
{
/* Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/* Battery Charging capability discovery finished Start Enumeration */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
/* Check for the Timeout, else start USB Device */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
return HAL_OK;
}
#endif /* defined (USB) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

658
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c Normal file
View File

@ -0,0 +1,658 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/de-initialization functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Defines PWR Private Defines
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enable access to the backup domain
* (RTC registers, RTC backup data registers).
* @note After reset, the backup domain is protected against
* possible unwanted write accesses.
* @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
* In order to set or modify the RTC clock, the backup domain access must be
* disabled.
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain
* (RTC registers, RTC backup data registers).
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
(+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** WakeUp pin configuration ***
================================
[..]
(+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
The polarity of these pins can be set to configure event detection on high
level (rising edge) or low level (falling edge).
*** Low Power modes configuration ***
=====================================
[..]
The devices feature 8 low-power modes:
(+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
(+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
(+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
(+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
(+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
*** Low-power run mode ***
==========================
[..]
(+) Entry: (from main run mode)
(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
(+) Exit:
(++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
then can the system clock frequency be increased above 2 MHz.
*** Sleep mode / Low-power sleep mode ***
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) WFI Exit:
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) or any wake-up event.
(+) WFE Exit:
(++) Any wake-up event such as an EXTI line configured in event mode.
[..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
the MCU is in Low-power Run mode.
*** Stop 0, Stop 1 and Stop 2 modes ***
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON
(++) PWR_LOWPOWERREGULATOR_ON
(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
(+) WFI Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt mode.
(++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
when programmed in wakeup mode.
(+) WFE Exit:
(++) Any EXTI Line (Internal or External) configured in Event mode.
[..]
When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
depending on the LPR bit setting.
When exiting Stop 2 mode, the MCU is in Run mode.
*** Standby mode ***
====================
[..]
The Standby mode offers two options:
(+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
and Standby circuitry.
(+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
SRAM and register contents are lost except for the RTC registers, RTC backup registers
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
to set RRS bit.
(++) Exit:
(+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin, IWDG reset.
[..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
*** Shutdown mode ***
======================
[..]
In Shutdown mode,
voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin.
[..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
* @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
* configuration information.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage thresholds corresponding to each
* detection level.
* @retval None
*/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS bits according to PVDLevel value */
MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
return HAL_OK;
}
/**
* @brief Enable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Disable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values which set the default polarity
* i.e. detection on high level (rising edge):
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
*
* or one of the following value where the user can explicitly specify the enabled pin and
* the chosen polarity:
* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
/* Specifies the Wake-Up pin polarity for the event detection
(rising or falling edge) */
MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
/* Enable wake-up pin */
SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
}
/**
* @brief Enter Sleep or Low-power Sleep mode.
* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
* @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
* in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
* to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
* Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
* Additionally, the clock frequency must be reduced below 2 MHz.
* Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
* be done before calling HAL_PWR_EnterSLEEPMode() API.
* @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
* Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
* @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
* @note When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Set Regulator parameter */
if (Regulator == PWR_MAINREGULATOR_ON)
{
/* If in low-power run mode at this point, exit it */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
{
if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
{
return ;
}
}
/* Regulator now in main mode. */
}
else
{
/* If in run mode, first move to low-power run mode.
The system clock frequency must be below 2 MHz at this point. */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
{
HAL_PWREx_EnableLowPowerRunMode();
}
}
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enter Stop mode
* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
* on devices where only "Stop mode" is mentioned with main or low power regulator ON.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
* the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
* (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
* after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
* only to the peripheral requesting it.
* SRAM1, SRAM2 and register contents are preserved.
* The BOR is available.
* The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
* @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
* is set; the MSI oscillator is selected if STOPWUCK is cleared.
* @note When the voltage regulator operates in low power mode (Stop 1), an additional
* startup delay is incurred when waking up.
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
* is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
* @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
if(Regulator == PWR_LOWPOWERREGULATOR_ON)
{
HAL_PWREx_EnterSTOP1Mode(STOPEntry);
}
else
{
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
}
}
/**
* @brief Enter Standby mode.
* @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
* off. The voltage regulator is disabled, except when SRAM2 content is preserved
* in which case the regulator is in low-power mode.
* SRAM1 and register contents are lost except for registers in the Backup domain and
* Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
* To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
* to set RRS bit.
* The BOR is available.
* @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
* Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
* same.
* These states are effective in Standby mode only if APC bit is set through
* HAL_PWREx_EnablePullUpPullDownConfig() API.
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Set Stand-by mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enable CORTEX M4 SEVONPEND bit.
* @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disable CORTEX M4 SEVONPEND bit.
* @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1474
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

1936
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c Normal file
View File

File diff suppressed because it is too large Load Diff

3552
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

7896
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c Normal file
View File

File diff suppressed because it is too large Load Diff

2841
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

4840
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c Normal file
View File

File diff suppressed because it is too large Load Diff

1074
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

2934
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c Normal file
View File

File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More