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Test with phase diff b/w CLK0 and CLK2

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This commit is contained in:
Thomas Kuschel
2022-06-06 22:33:30 +02:00
parent 86ef8e7049
commit a3fcd0e57c
9 changed files with 356 additions and 18 deletions
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29
Core/Inc/commands.h Normal file
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@ -0,0 +1,29 @@
/**
******************************************************************************
* @file commands.h
* @brief Header for command.c file, the command interpreter, a generic one
******************************************************************************
* @author: Thomas Kuschel KW4NZ
* created 2022-06-04
*
******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __COMMANDS_H_
#define __COMMANDS_H_
#ifdef __cplusplus
extern "C" {
#endif
//struct command_ctx_s *command_inst;
typedef struct command_ctx_s *command_inst_t;
/* function prototypes */
int not_implemented(command_inst_t inst, char *args);
#ifdef __cplusplus
}
#endif
#endif /* __COMMANDS_H_ */

5
Core/Inc/stm32_si5351.h
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@ -133,12 +133,15 @@ typedef enum {
/* Exported functions --------------------------------------------------------*/
si5351_inst_t si5351_init(void * i2c_handle, uint32_t xtal_frequency, uint8_t i2c_address, size_t datasize);
int si5351_deinit(si5351_inst_t si5351_handle);
int si5351_isready(si5351_inst_t inst);
int si5351_i2c_ready(si5351_inst_t inst);
int si5351_program(si5351_inst_t inst);
int si5351_enable_output(si5351_inst_t inst, uint8_t clk);
int si5351_disable_output(si5351_inst_t inst, uint8_t clk);
int si5351_set_clk0(si5351_inst_t inst, uint32_t frequency);
int si5351_set_clk(si5351_inst_t inst, uint32_t frequency, uint8_t clk, si5351_pll_t pll);
int si5351_set_clk_phase(si5351_inst_t inst, uint32_t frequency, double phase, uint8_t clk, si5351_pll_t pll);
int si5351_set_phase(si5351_inst_t inst, uint8_t phase, uint8_t clk);
#if SI5351_DEFAULTS
si5351_inst_t si5351_initialize(void * i2c_handle);

59
Core/Inc/stm32_si5351_reg.h
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@ -1073,6 +1073,65 @@ even integers greater than or equal to 6. All other divide values are invalid. *
#define R6_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */
#define R6_DIV (7u<<4)
/* Spread Spectrum Parameters
* Registers 149 upto 161
*/
/* VCXO Parameters
* Registers 162 upto 164
*/
/* CLK0 Initial Phase Offset
* CLK0_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK0_INITIAL_PHASE_OFFSET 165u /* R/W */
#define CLKx_PHOFF_RESERVED (0u<<7) /* 0b: Only write 0 to this bit */
#define CLKx_PHOFF_6 (1u<<6)
#define CLKx_PHOFF_5 (1u<<5)
#define CLKx_PHOFF_4 (1u<<4)
#define CLKx_PHOFF_3 (1u<<3)
#define CLKx_PHOFF_2 (1u<<2)
#define CLKx_PHOFF_1 (1u<<1)
#define CLKx_PHOFF_0 (1u<<0)
#define CLKx_PHOFF (0x7F)
#define CLK0_PHOFF CLKx_PHOFF
/* CLK1 Initial Phase Offset
* CLK1_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK1_INITIAL_PHASE_OFFSET 166u /* R/W */
#define CLK1_PHOFF CLKx_PHOFF
/* CLK2 Initial Phase Offset
* CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK2_INITIAL_PHASE_OFFSET 167u /* R/W */
#define CLK2_PHOFF CLKx_PHOFF
/* CLK2 Initial Phase Offset
* CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK3_INITIAL_PHASE_OFFSET 168u /* R/W */
#define CLK3_PHOFF CLKx_PHOFF
/* CLK3 Initial Phase Offset
* CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK4_INITIAL_PHASE_OFFSET 169u /* R/W */
#define CLK4_PHOFF CLKx_PHOFF
/* CLK4 Initial Phase Offset
* CLK4_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of Tvco/4, where
* Tvco is the period of the VCO/PLL associated with this output.
*/
#define SI5351_CLK5_INITIAL_PHASE_OFFSET 170u /* R/W */
#define CLK5_PHOFF CLKx_PHOFF
/* PLL Reset
* Resets the PLLA, PLLB when writing an 1 to the corresponding bit
* Leave the reserved bits as default.