From acc0f0a5da1e1c1d0e516e28a17b45bbf4b2ab9b Mon Sep 17 00:00:00 2001 From: Tom Kuschel Date: Mon, 16 May 2022 01:47:12 +0200 Subject: [PATCH] ADD read and write wrapper function for i2c bus, start programming procedure for si5351 --- Core/Inc/stm32_si5351.h | 10 +- Core/Inc/stm32_si5351_reg.h | 1081 +++++++++++++++++++++++++++++++++++ Core/Src/main.c | 6 +- Core/Src/stm32_si5351.c | 78 ++- 4 files changed, 1162 insertions(+), 13 deletions(-) create mode 100644 Core/Inc/stm32_si5351_reg.h diff --git a/Core/Inc/stm32_si5351.h b/Core/Inc/stm32_si5351.h index 44993e7..4fc4a4c 100644 --- a/Core/Inc/stm32_si5351.h +++ b/Core/Inc/stm32_si5351.h @@ -81,7 +81,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include - +#include /* register map of the Si5351 */ /* Private includes ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -89,14 +89,17 @@ extern "C" { typedef struct __SI5351_HandleTypeDef *si5351_inst_t; /* Exported constants --------------------------------------------------------*/ -/** @enum errno_t Error Number Constants +/** @enum errno_t Error Number Constants, @TODO could also errno.h included!! */ typedef enum { EPERM = 1, /*!< Operation not permitted */ + EIO = 5, /*!< I/O error */ ENOMEM = 12, /*!< Out of memory */ ENODEV = 19, /*!< No such device */ + EBUSY = 16, /*!< Device or resource busy */ EINVAL = 22, /*!< Invalid argument */ - EADDRINUSE = 98 /*!< Address already in use */ + EADDRINUSE = 98,/*!< Address already in use */ + ETIMEDOUT = 116 /*!< Connection timed out */ } si5351_errno_t; /* Exported variables --------------------------------------------------------*/ @@ -107,6 +110,7 @@ typedef enum { si5351_inst_t si5351_init(void * i2c_handle, uint32_t xtal_frequency, uint8_t i2c_address); int si5351_deinit(si5351_inst_t si5351_handle); int si5351_isready(si5351_inst_t inst); +int si5351_program(si5351_inst_t inst); #ifdef __cplusplus } /* extern "C" */ diff --git a/Core/Inc/stm32_si5351_reg.h b/Core/Inc/stm32_si5351_reg.h new file mode 100644 index 0000000..674fcf3 --- /dev/null +++ b/Core/Inc/stm32_si5351_reg.h @@ -0,0 +1,1081 @@ +/* Register Map for the Si5351 Devices */ +/* */ +/* Thomas Kuschel created 2022-05-10 */ +/* KW4NZ Version 1.0 */ + +#define SI5351_DEVICE_STATUS 0u /* R */ +#define SI5351_SYS_INIT (1u<<7) /* System Initialization Status, 0..System initialization is complete. Device is ready 1..Device is in system initalization mode. */ +#define SI5351_LOL_B (1u<<6) /* PLL B Loss Of Lock Status, 0..PLL B is locked, 1..PLL B is unlocked. */ +#define SI5351_LOL_A (1u<<5) /* PLL A Loss Of Lock Status */ +#define SI5351_LOS_CLKIN (1u<<4) /* CLKIN Loss Of Lock Status (Si5351 only) 0..Valid clock signal at the CLKIN pin */ +#define SI5351_LOS_XTAL (1u<<3) /* Crystal Loss Of Signal. 0..Valid crystal signal at the XA and XB Pins */ +#define SI5351_REVID_1 (1u<<1) +#define SI5351_REVID_0 (1u<<0) +#define SI5351_REVID (3u<<0) /* Revision number of the device. */ +#define SI5351_DEVICE_STATUS_RESET_VALUE 0x00 + +#define SI5351_INTERRUPT_STATUS_STICKY 1u /* R/W */ +#define SI5351_SYS_INIT_STKY (1u<<7) /* System Calibration Status Sticky Bit. 0..No SYS_INIT interrupt has occured since it was last cleared. */ +#define SI5351_LOL_B_STKY (1u<<6) /* PLLB Loss of Lock Status Sticky Bit. 0..No PLL_B interrupt has occured since it was last cleared. */ +#define SI5351_LOL_A_STKY (1u<<5) +#define SI5351_LOS_CLKIN_STKY (1u<<4) +#define SI5351_LOS_XTAL_STKY (1u<<3) +#define SI5351_INTERRUPT_STATUS_STICKY_RESET_VALUE 0x00 + +#define SI5351_INTERRUPT_STATUS_MASK 2u +#define SI5351_SYS_INIT_MASK (1u<<7) +#define SI5351_LOL_B_MASK (1u<<6) +#define SI5351_LOL_A_MASK (1u<<5) +#define SI5351_LOS_CLKIN_MASK (1u<<4) +#define SI5351_LOS_XTAL_MASK (1u<<3) +#define SI5351_INTERRUPT_STATUS_MASK_RESET_VALUE 0x00 + +#define SI5351_OUTPUT_ENABLE_CONTROL 3u /* R/W */ +#define SI5351_CLK7_OEB (1u<<7) /* Output Disable for CLKx. 0..Enable CLKx output. 1..Disable CLKx output. */ +#define SI5351_CLK6_OEB (1u<<6) +#define SI5351_CLK5_OEB (1u<<5) +#define SI5351_CLK4_OEB (1u<<4) +#define SI5351_CLK3_OEB (1u<<3) +#define SI5351_CLK2_OEB (1u<<2) +#define SI5351_CLK1_OEB (1u<<1) +#define SI5351_CLK0_OEB (1u<<0) +#define SI5351_OUTPUT_ENABLE_CONTROL_RESET_VALUE 0x00 + +#define SI5351_OEB_PIN_ENABLE_CONTROL_MASK 9u /* R/W */ +#define SI5351_OEB_MASK7 (1u<<7) /* OEB pin enable control of CLKx. 0..OEB pin controls enable/disable state of CLKx output */ +#define SI5351_OEB_MASK6 (1u<<6) /* 1..OEB pin does not control enable/disable state of CLKx output. */ +#define SI5351_OEB_MASK5 (1u<<5) +#define SI5351_OEB_MASK4 (1u<<4) +#define SI5351_OEB_MASK3 (1u<<3) +#define SI5351_OEB_MASK2 (1u<<2) +#define SI5351_OEB_MASK1 (1u<<1) +#define SI5351_OEB_MASK0 (1u<<0) +#define SI5351_OEB_PIN_ENABLE_CONTROL_MASK_RESET_VALUE 0x00 + +#define SI5351_PLL_INPUT_SOURCE 15u /* R/W */ +#define SI5351_CLKIN_DIV_1 (1u<<7) +#define SI5351_CLKIN_DIV_0 (1u<<6) +#define SI5351_CLKIN_DIV (3u<<6) /* CLKIN Input Divider 00b: Devide by 1. 01b: Divide by 2. 10b: Divide by 4. 11b: Divide by 8. */ +#define SI5351_PLLB_SRC (1u<<3) /* Input Source Select for PLLB. 0..Select the XTAL input as the reference clock for PLLB */ +#define SI5351_PLLA_SRC (1u<<2) /* Input Source Select for PLLA. */ +#define SI5351_PLL_INPUT_SOURCE_RESET_VALUE 0x00 + +#define SI5351_CLK0_CONTROL 16u /* R/W */ +#define SI5351_CLK0_PDN (1u<<7) /* Clock 0 Power Down. */ +#define SI5351_MS0_INT (1u<<6) /* MultiSynth 0 Integer Mode. 1..MS0 operates in integer mode. */ +#define SI5351_MS0_SRC (1u<<5) /* MultiSynth Source Select for CLK0 */ +#define SI5351_CLK0_INV (1u<<4) /* Output Clock 0 Invert. */ +#define SI5351_CLK0_SRC_1 (1u<<3) /* Output Clock 0 Input Source */ +#define SI5351_CLK0_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK0. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK0_SRC (3u<<2) /* and connects CLK0 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK0_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK0. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 0 as source for CLK0 */ +#define SI5351_CLK0_IDRV_0 (1u<<0) /* CLK0 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK0_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK0_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK1_CONTROL 17u /* R/W */ +#define SI5351_CLK1_PDN (1u<<7) /* Clock 1 Power Down. */ +#define SI5351_MS1_INT (1u<<6) /* MultiSynth 1 Integer Mode. 1..MS1 operates in integer mode. */ +#define SI5351_MS1_SRC (1u<<5) /* MultiSynth Source Select for CLK1 */ +#define SI5351_CLK1_INV (1u<<4) /* Output Clock 1 Invert. */ +#define SI5351_CLK1_SRC_1 (1u<<3) /* Output Clock 1 Input Source */ +#define SI5351_CLK1_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK0. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK1_SRC (3u<<2) /* and connects CLK1 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK1_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK1. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 1 as source for CLK1 */ +#define SI5351_CLK1_IDRV_0 (1u<<0) /* CLK1 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK1_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK1_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK2_CONTROL 18u /* R/W */ +#define SI5351_CLK2_PDN (1u<<7) /* Clock 2 Power Down. */ +#define SI5351_MS2_INT (1u<<6) /* MultiSynth 2 Integer Mode. 1..MS2 operates in integer mode. */ +#define SI5351_MS2_SRC (1u<<5) /* MultiSynth Source Select for CLK2 */ +#define SI5351_CLK2_INV (1u<<4) /* Output Clock 2 Invert. */ +#define SI5351_CLK2_SRC_1 (1u<<3) /* Output Clock 2 Input Source */ +#define SI5351_CLK2_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK2. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK2_SRC (3u<<2) /* and connects CLK2 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK2_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK2. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 2 as source for CLK2 */ +#define SI5351_CLK2_IDRV_0 (1u<<0) /* CLK2 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK2_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK2_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK3_CONTROL 19u /* R/W */ +#define SI5351_CLK3_PDN (1u<<7) /* Clock 3 Power Down. */ +#define SI5351_MS3_INT (1u<<6) /* MultiSynth 3 Integer Mode. 1..MS3 operates in integer mode. */ +#define SI5351_MS3_SRC (1u<<5) /* MultiSynth Source Select for CLK3 */ +#define SI5351_CLK3_INV (1u<<4) /* Output Clock 3 Invert. */ +#define SI5351_CLK3_SRC_1 (1u<<3) /* Output Clock 3 Input Source */ +#define SI5351_CLK3_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK3. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK3_SRC (3u<<2) /* and connects CLK3 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK3_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK3. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 3 as source for CLK3 */ +#define SI5351_CLK3_IDRV_0 (1u<<0) /* CLK3 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK3_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK3_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK4_CONTROL 20u /* R/W */ +#define SI5351_CLK4_PDN (1u<<7) /* Clock 4 Power Down. */ +#define SI5351_MS4_INT (1u<<6) /* MultiSynth 4 Integer Mode. 1..MS4 operates in integer mode. */ +#define SI5351_MS4_SRC (1u<<5) /* MultiSynth Source Select for CLK4 */ +#define SI5351_CLK4_INV (1u<<4) /* Output Clock 4 Invert. */ +#define SI5351_CLK4_SRC_1 (1u<<3) /* Output Clock 4 Input Source */ +#define SI5351_CLK4_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK4. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK4_SRC (3u<<2) /* and connects CLK4 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK4_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK4. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 4 as source for CLK4 */ +#define SI5351_CLK4_IDRV_0 (1u<<0) /* CLK4 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK4_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK4_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK5_CONTROL 21u /* R/W */ +#define SI5351_CLK5_PDN (1u<<7) /* Clock 5 Power Down. */ +#define SI5351_MS5_INT (1u<<6) /* MultiSynth 5 Integer Mode. 1..MS5 operates in integer mode. */ +#define SI5351_MS5_SRC (1u<<5) /* MultiSynth Source Select for CLK5 */ +#define SI5351_CLK5_INV (1u<<4) /* Output Clock 5 Invert. */ +#define SI5351_CLK5_SRC_1 (1u<<3) /* Output Clock 5 Input Source */ +#define SI5351_CLK5_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK5. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK5_SRC (3u<<2) /* and connects CLK5 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK5_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK5. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 5 as source for CLK5 */ +#define SI5351_CLK5_IDRV_0 (1u<<0) /* CLK5 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK5_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK5_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK6_CONTROL 22u /* R/W */ +#define SI5351_CLK6_PDN (1u<<7) /* Clock 6 Power Down. */ +#define SI5351_MS6_INT (1u<<6) /* MultiSynth 6 Integer Mode. 1..MS6 operates in integer mode. */ +#define SI5351_MS6_SRC (1u<<5) /* MultiSynth Source Select for CLK6 */ +#define SI5351_CLK6_INV (1u<<4) /* Output Clock 6 Invert. */ +#define SI5351_CLK6_SRC_1 (1u<<3) /* Output Clock 6 Input Source */ +#define SI5351_CLK6_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK6. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK6_SRC (3u<<2) /* and connects CLK6 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK6_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK6. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 6 as source for CLK6 */ +#define SI5351_CLK6_IDRV_0 (1u<<0) /* CLK6 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK6_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK6_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK7_CONTROL 23u /* R/W */ +#define SI5351_CLK7_PDN (1u<<7) /* Clock 7 Power Down. */ +#define SI5351_MS7_INT (1u<<6) /* MultiSynth 7 Integer Mode. 1..MS7 operates in integer mode. */ +#define SI5351_MS7_SRC (1u<<5) /* MultiSynth Source Select for CLK7 */ +#define SI5351_CLK7_INV (1u<<4) /* Output Clock 7 Invert. */ +#define SI5351_CLK7_SRC_1 (1u<<3) /* Output Clock 7 Input Source */ +#define SI5351_CLK7_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK7. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */ +#define SI5351_CLK7_SRC (3u<<2) /* and connects CLK7 directly to the oscillator which generates an output freq determined by the XTAL freq. */ +#define SI5351_CLK7_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK7. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 7 as source for CLK7 */ +#define SI5351_CLK7_IDRV_0 (1u<<0) /* CLK7 Output Rise and Fall time / Drive Strength Control */ +#define SI5551_CLK7_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */ +#define SI5351_CLK7_CONTROL_RESET_VALUE 0x00 + +#define SI5351_CLK3_0_DISABLE_STATE 24u /* R/W */ +#define SI5351_CLK3_DIS_STATE_1 (1u<<7) /* Clock x Disable State 00: CLKx is set to a LOW state when disabled, */ +#define SI5351_CLK3_DIS_STATE_0 (1u<<6) /* 01: CLKx is set to a HIGH state when disabled, */ +#define SI5351_CLK3_DIS_STATE (3u<<6) /* 10: CLKx is set to a HIGH IMPEDANCE state when disabled, */ +#define SI5351_CLK2_DIS_STATE_1 (1u<<5) /* 11: CLKx is NEVER DISABLED */ +#define SI5351_CLK2_DIS_STATE_0 (1u<<4) +#define SI5351_CLK2_DIS_STATE (3u<<4) +#define SI5351_CLK1_DIS_STATE_1 (1u<<3) +#define SI5351_CLK1_DIS_STATE_0 (1u<<2) +#define SI5351_CLK1_DIS_STATE (3u<<2) +#define SI5351_CLK0_DIS_STATE_1 (1u<<1) +#define SI5351_CLK0_DIS_STATE_0 (1u<<0) +#define SI5351_CLK0_DIS_STATE (3u<<0) +#define SI5351_CLK3_0_DISABLE_STATE_RESET_VALUE 0x00 + +#define SI5351_CLK7_4_DISABLE_STATE 25u /* R/W */ +#define SI5351_CLK7_DIS_STATE_1 (1u<<7) /* Clock x Disable State 00: CLKx is set to a LOW state when disabled, */ +#define SI5351_CLK7_DIS_STATE_0 (1u<<6) /* 01: CLKx is set to a HIGH state when disabled, */ +#define SI5351_CLK7_DIS_STATE (3u<<6) /* 10: CLKx is set to a HIGH IMPEDANCE state when disabled, */ +#define SI5351_CLK6_DIS_STATE_1 (1u<<5) /* 11: CLKx is NEVER DISABLED */ +#define SI5351_CLK6_DIS_STATE_0 (1u<<4) +#define SI5351_CLK6_DIS_STATE (3u<<4) +#define SI5351_CLK5_DIS_STATE_1 (1u<<3) +#define SI5351_CLK5_DIS_STATE_0 (1u<<2) +#define SI5351_CLK5_DIS_STATE (3u<<2) +#define SI5351_CLK4_DIS_STATE_1 (1u<<1) +#define SI5351_CLK4_DIS_STATE_0 (1u<<0) +#define SI5351_CLK4_DIS_STATE (3u<<0) +#define SI5351_CLK4_0_DISABLE_STATE_RESET_VALUE 0x00 + +/* Multisynth NA Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the PLLA Feedback Multisynth Divider. */ + +#define SI5351_MULTISYNTH_NA_PARAMETER_3_HI 26u /* R/W */ +#define MSNA_P3_15 (1u<<7) +#define MSNA_P3_14 (1u<<6) +#define MSNA_P3_13 (1u<<5) +#define MSNA_P3_12 (1u<<4) +#define MSNA_P3_11 (1u<<3) +#define MSNA_P3_10 (1u<<2) +#define MSNA_P3_9 (1u<<1) +#define MSNA_P3_8 (1u<<0) +#define MSNA_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH_NA_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH_NA_PARAMETER_3_LO 27u /* R/W */ +#define MSNA_P3_7 (1u<<7) +#define MSNA_P3_6 (1u<<6) +#define MSNA_P3_5 (1u<<5) +#define MSNA_P3_4 (1u<<4) +#define MSNA_P3_3 (1u<<3) +#define MSNA_P3_2 (1u<<2) +#define MSNA_P3_1 (1u<<1) +#define MSNA_P3_0 (1u<<0) +#define MSNA_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NA_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth NA Parameter 1. +This 18-bit number is an encoded representation of the integer part of the PLLA +Feedback Multisynth divider. */ + +#define SI5351_MULTISYNTH_NA_PARAMETER_1_HIHI 28u /* R/W */ +#define MSNA_P1_17 (1u<<1) +#define MSNA_P1_16 (1u<<0) +#define MSNA_P1_17_16 (3u<<0) + +#define SI5351_MULTISYNTH_NA_PARAMETER_1_HI 29u /* R/W */ +#define MSNA_P1_15 (1u<<7) +#define MSNA_P1_14 (1u<<6) +#define MSNA_P1_13 (1u<<5) +#define MSNA_P1_12 (1u<<4) +#define MSNA_P1_11 (1u<<3) +#define MSNA_P1_10 (1u<<2) +#define MSNA_P1_9 (1u<<1) +#define MSNA_P1_8 (1u<<0) +#define MSNA_P1_15_8 (0xFF) + +#define SI5351_MULTISYNTH_NA_PARAMETER_1_LO 30u /* R/W */ +#define MSNA_P1_7 (1u<<7) +#define MSNA_P1_6 (1u<<6) +#define MSNA_P1_5 (1u<<5) +#define MSNA_P1_4 (1u<<4) +#define MSNA_P1_3 (1u<<3) +#define MSNA_P1_2 (1u<<2) +#define MSNA_P1_1 (1u<<1) +#define MSNA_P1_0 (1u<<0) +#define MSNA_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NA_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH_NA_PARAMETER_3_2_HIHI 31u /* R/W */ +#define MSNA_P3_19 (1u<<7) +#define MSNA_P3_18 (1u<<6) +#define MSNA_P3_17 (1u<<5) +#define MSNA_P3_16 (1u<<4) +#define MSNA_P3_19_16 (7u<<4) +#define MSNA_P2_19 (1u<<3) +#define MSNA_P2_18 (1u<<2) +#define MSNA_P2_17 (1u<<1) +#define MSNA_P2_16 (1u<<0) +#define MSNA_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH_NA_PARAMETER_2_HI 32u /* R/W */ +#define MSNA_P2_15 (1u<<7) +#define MSNA_P2_14 (1u<<6) +#define MSNA_P2_13 (1u<<5) +#define MSNA_P2_12 (1u<<4) +#define MSNA_P2_11 (1u<<3) +#define MSNA_P2_10 (1u<<2) +#define MSNA_P2_9 (1u<<1) +#define MSNA_P2_8 (1u<<0) +#define MSNA_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH_NA_PARAMETER_2_LO 33u /* R/W */ +#define MSNA_P2_7 (1u<<7) +#define MSNA_P2_6 (1u<<6) +#define MSNA_P2_5 (1u<<5) +#define MSNA_P2_4 (1u<<4) +#define MSNA_P2_3 (1u<<3) +#define MSNA_P2_2 (1u<<2) +#define MSNA_P2_1 (1u<<1) +#define MSNA_P2_0 (1u<<0) +#define MSNA_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NA_PARAMETER_2_LO_RESET_VALUE 0xXX */ + +/* Multisynth NB Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the PLLB Feedback Multisynth divider. */ + +#define SI5351_MULTISYNTH_NB_PARAMETER_3_HI 34u /* R/W */ +#define MSNB_P3_15 (1u<<7) +#define MSNB_P3_14 (1u<<6) +#define MSNB_P3_13 (1u<<5) +#define MSNB_P3_12 (1u<<4) +#define MSNB_P3_11 (1u<<3) +#define MSNB_P3_10 (1u<<2) +#define MSNB_P3_9 (1u<<1) +#define MSNB_P3_8 (1u<<0) +#define MSNB_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH_NB_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH_NB_PARAMETER_3_LO 35u /* R/W */ +#define MSNB_P3_7 (1u<<7) +#define MSNB_P3_6 (1u<<6) +#define MSNB_P3_5 (1u<<5) +#define MSNB_P3_4 (1u<<4) +#define MSNB_P3_3 (1u<<3) +#define MSNB_P3_2 (1u<<2) +#define MSNB_P3_1 (1u<<1) +#define MSNB_P3_0 (1u<<0) +#define MSNB_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NB_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth NB Parameter 1. +This 18-bit number is an encoded representation of the integer part of the PLLA +Feedback Multisynth divider. */ + +#define SI5351_MULTISYNTH_NB_PARAMETER_1_HIHI 36u /* R/W */ +#define MSNB_P1_17 (1u<<1) +#define MSNB_P1_16 (1u<<0) +#define MSNB_P1_17_16 (3u<<0) + +#define SI5351_MULTISYNTH_NB_PARAMETER_1_HI 37u /* R/W */ +#define MSNB_P1_15 (1u<<7) +#define MSNB_P1_14 (1u<<6) +#define MSNB_P1_13 (1u<<5) +#define MSNB_P1_12 (1u<<4) +#define MSNB_P1_11 (1u<<3) +#define MSNB_P1_10 (1u<<2) +#define MSNB_P1_9 (1u<<1) +#define MSNB_P1_8 (1u<<0) +#define MSNB_P1_15_8 (0xFF) + +#define SI5351_MULTISYNTH_NB_PARAMETER_1_LO 38u /* R/W */ +#define MSNB_P1_7 (1u<<7) +#define MSNB_P1_6 (1u<<6) +#define MSNB_P1_5 (1u<<5) +#define MSNB_P1_4 (1u<<4) +#define MSNB_P1_3 (1u<<3) +#define MSNB_P1_2 (1u<<2) +#define MSNB_P1_1 (1u<<1) +#define MSNB_P1_0 (1u<<0) +#define MSNB_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NB_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH_NB_PARAMETER_3_2_HIHI 39u /* R/W */ +#define MSNB_P3_19 (1u<<7) +#define MSNB_P3_18 (1u<<6) +#define MSNB_P3_17 (1u<<5) +#define MSNB_P3_16 (1u<<4) +#define MSNB_P3_19_16 (7u<<4) +#define MSNB_P2_19 (1u<<3) +#define MSNB_P2_18 (1u<<2) +#define MSNB_P2_17 (1u<<1) +#define MSNB_P2_16 (1u<<0) +#define MSNB_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH_NB_PARAMETER_2_HI 40u /* R/W */ +#define MSNB_P2_15 (1u<<7) +#define MSNB_P2_14 (1u<<6) +#define MSNB_P2_13 (1u<<5) +#define MSNB_P2_12 (1u<<4) +#define MSNB_P2_11 (1u<<3) +#define MSNB_P2_10 (1u<<2) +#define MSNB_P2_9 (1u<<1) +#define MSNB_P2_8 (1u<<0) +#define MSNB_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH_NB_PARAMETER_2_LO 41u /* R/W */ +#define MSNB_P2_7 (1u<<7) +#define MSNB_P2_6 (1u<<6) +#define MSNB_P2_5 (1u<<5) +#define MSNB_P2_4 (1u<<4) +#define MSNB_P2_3 (1u<<3) +#define MSNB_P2_2 (1u<<2) +#define MSNB_P2_1 (1u<<1) +#define MSNB_P2_0 (1u<<0) +#define MSNB_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH_NB_PARAMETER_2_LO_RESET_VALUE 0xXX */ + +/* Multisynth0 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth0 Divider. */ + +#define SI5351_MULTISYNTH0_PARAMETER_3_HI 42u /* R/W */ +#define MS0_P3_15 (1u<<7) +#define MS0_P3_14 (1u<<6) +#define MS0_P3_13 (1u<<5) +#define MS0_P3_12 (1u<<4) +#define MS0_P3_11 (1u<<3) +#define MS0_P3_10 (1u<<2) +#define MS0_P3_9 (1u<<1) +#define MS0_P3_8 (1u<<0) +#define MS0_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH0_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH0_PARAMETER_3_LO 43u /* R/W */ +#define MS0_P3_7 (1u<<7) +#define MS0_P3_6 (1u<<6) +#define MS0_P3_5 (1u<<5) +#define MS0_P3_4 (1u<<4) +#define MS0_P3_3 (1u<<3) +#define MS0_P3_2 (1u<<2) +#define MS0_P3_1 (1u<<1) +#define MS0_P3_0 (1u<<0) +#define MS0_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH0_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth0 Parameters R0 Output Divider, MS0 Divide by 4 Enable, + * Multisynth0 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth0 divider. */ + +#define SI5351_MULTISYNTH0_PARAMETER_DIV 44u /* R/W */ +#define R0_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R0_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R0_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R0_DIV (7u<<4) +#define MS0_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS0_DIVBY4_0 (1u<<2) +#define MS0_DIVBY4 (3u<<2) +#define MS0_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS0_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS0_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH0_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH0_PARAMETER_1_HI 45u /* R/W */ +#define MS0_P1_15 (1u<<7) +#define MS0_P1_14 (1u<<6) +#define MS0_P1_13 (1u<<5) +#define MS0_P1_12 (1u<<4) +#define MS0_P1_11 (1u<<3) +#define MS0_P1_10 (1u<<2) +#define MS0_P1_9 (1u<<1) +#define MS0_P1_8 (1u<<0) +#define MS0_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH0_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH0_PARAMETER_1_LO 46u /* R/W */ +#define MS0_P1_7 (1u<<7) +#define MS0_P1_6 (1u<<6) +#define MS0_P1_5 (1u<<5) +#define MS0_P1_4 (1u<<4) +#define MS0_P1_3 (1u<<3) +#define MS0_P1_2 (1u<<2) +#define MS0_P1_1 (1u<<1) +#define MS0_P1_0 (1u<<0) +#define MS0_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH0_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH0_PARAMETER_3_2_HIHI 47u /* R/W */ +#define MS0_P3_19 (1u<<7) +#define MS0_P3_18 (1u<<6) +#define MS0_P3_17 (1u<<5) +#define MS0_P3_16 (1u<<4) +#define MS0_P3_19_16 (7u<<4) +#define MS0_P2_19 (1u<<3) +#define MS0_P2_18 (1u<<2) +#define MS0_P2_17 (1u<<1) +#define MS0_P2_16 (1u<<0) +#define MS0_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH0_PARAMETER_2_HI 48u /* R/W */ +#define MS0_P2_15 (1u<<7) +#define MS0_P2_14 (1u<<6) +#define MS0_P2_13 (1u<<5) +#define MS0_P2_12 (1u<<4) +#define MS0_P2_11 (1u<<3) +#define MS0_P2_10 (1u<<2) +#define MS0_P2_9 (1u<<1) +#define MS0_P2_8 (1u<<0) +#define MS0_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH0_PARAMETER_2_LO 49u /* R/W */ +#define MS0_P2_7 (1u<<7) +#define MS0_P2_6 (1u<<6) +#define MS0_P2_5 (1u<<5) +#define MS0_P2_4 (1u<<4) +#define MS0_P2_3 (1u<<3) +#define MS0_P2_2 (1u<<2) +#define MS0_P2_1 (1u<<1) +#define MS0_P2_0 (1u<<0) +#define MS0_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH0_PARAMETER_2_LO_RESET_VALUE 0xXX */ + +/* Multisynth1 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth1 Divider. */ + +#define SI5351_MULTISYNTH1_PARAMETER_3_HI 50u /* R/W */ +#define MS1_P3_15 (1u<<7) +#define MS1_P3_14 (1u<<6) +#define MS1_P3_13 (1u<<5) +#define MS1_P3_12 (1u<<4) +#define MS1_P3_11 (1u<<3) +#define MS1_P3_10 (1u<<2) +#define MS1_P3_9 (1u<<1) +#define MS1_P3_8 (1u<<0) +#define MS1_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH1_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH1_PARAMETER_3_LO 51u /* R/W */ +#define MS1_P3_7 (1u<<7) +#define MS1_P3_6 (1u<<6) +#define MS1_P3_5 (1u<<5) +#define MS1_P3_4 (1u<<4) +#define MS1_P3_3 (1u<<3) +#define MS1_P3_2 (1u<<2) +#define MS1_P3_1 (1u<<1) +#define MS1_P3_0 (1u<<0) +#define MS1_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH1_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth1 Parameters R1 Output Divider, MS1 Divide by 4 Enable, + * Multisynth1 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth1 divider. */ + +#define SI5351_MULTISYNTH1_PARAMETER_DIV 52u /* R/W */ +#define R1_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R1_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R1_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R1_DIV (7u<<4) +#define MS1_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS1_DIVBY4_0 (1u<<2) +#define MS1_DIVBY4 (3u<<2) +#define MS1_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS1_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS1_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH1_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH1_PARAMETER_1_HI 53u /* R/W */ +#define MS1_P1_15 (1u<<7) +#define MS1_P1_14 (1u<<6) +#define MS1_P1_13 (1u<<5) +#define MS1_P1_12 (1u<<4) +#define MS1_P1_11 (1u<<3) +#define MS1_P1_10 (1u<<2) +#define MS1_P1_9 (1u<<1) +#define MS1_P1_8 (1u<<0) +#define MS1_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH1_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH1_PARAMETER_1_LO 54u /* R/W */ +#define MS1_P1_7 (1u<<7) +#define MS1_P1_6 (1u<<6) +#define MS1_P1_5 (1u<<5) +#define MS1_P1_4 (1u<<4) +#define MS1_P1_3 (1u<<3) +#define MS1_P1_2 (1u<<2) +#define MS1_P1_1 (1u<<1) +#define MS1_P1_0 (1u<<0) +#define MS1_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH1_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH1_PARAMETER_3_2_HIHI 55u /* R/W */ +#define MS1_P3_19 (1u<<7) +#define MS1_P3_18 (1u<<6) +#define MS1_P3_17 (1u<<5) +#define MS1_P3_16 (1u<<4) +#define MS1_P3_19_16 (7u<<4) +#define MS1_P2_19 (1u<<3) +#define MS1_P2_18 (1u<<2) +#define MS1_P2_17 (1u<<1) +#define MS1_P2_16 (1u<<0) +#define MS1_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH1_PARAMETER_2_HI 56u /* R/W */ +#define MS1_P2_15 (1u<<7) +#define MS1_P2_14 (1u<<6) +#define MS1_P2_13 (1u<<5) +#define MS1_P2_12 (1u<<4) +#define MS1_P2_11 (1u<<3) +#define MS1_P2_10 (1u<<2) +#define MS1_P2_9 (1u<<1) +#define MS1_P2_8 (1u<<0) +#define MS1_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH1_PARAMETER_2_LO 57u /* R/W */ +#define MS1_P2_7 (1u<<7) +#define MS1_P2_6 (1u<<6) +#define MS1_P2_5 (1u<<5) +#define MS1_P2_4 (1u<<4) +#define MS1_P2_3 (1u<<3) +#define MS1_P2_2 (1u<<2) +#define MS1_P2_1 (1u<<1) +#define MS1_P2_0 (1u<<0) +#define MS1_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH1_PARAMETER_2_LO_RESET_VALUE 0xXX */ + + + + + +/* Multisynth2 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth2 Divider. */ + +#define SI5351_MULTISYNTH2_PARAMETER_3_HI 58u /* R/W */ +#define MS2_P3_15 (1u<<7) +#define MS2_P3_14 (1u<<6) +#define MS2_P3_13 (1u<<5) +#define MS2_P3_12 (1u<<4) +#define MS2_P3_11 (1u<<3) +#define MS2_P3_10 (1u<<2) +#define MS2_P3_9 (1u<<1) +#define MS2_P3_8 (1u<<0) +#define MS2_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH2_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH2_PARAMETER_3_LO 59u /* R/W */ +#define MS2_P3_7 (1u<<7) +#define MS2_P3_6 (1u<<6) +#define MS2_P3_5 (1u<<5) +#define MS2_P3_4 (1u<<4) +#define MS2_P3_3 (1u<<3) +#define MS2_P3_2 (1u<<2) +#define MS2_P3_1 (1u<<1) +#define MS2_P3_0 (1u<<0) +#define MS2_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH2_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth2 Parameters R2 Output Divider, MS2 Divide by 4 Enable, + * Multisynth2 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth2 divider. */ + +#define SI5351_MULTISYNTH2_PARAMETER_DIV 60u /* R/W */ +#define R2_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R2_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R2_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R2_DIV (7u<<4) +#define MS2_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS2_DIVBY4_0 (1u<<2) +#define MS2_DIVBY4 (3u<<2) +#define MS2_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS2_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS2_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH2_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH2_PARAMETER_1_HI 61u /* R/W */ +#define MS2_P1_15 (1u<<7) +#define MS2_P1_14 (1u<<6) +#define MS2_P1_13 (1u<<5) +#define MS2_P1_12 (1u<<4) +#define MS2_P1_11 (1u<<3) +#define MS2_P1_10 (1u<<2) +#define MS2_P1_9 (1u<<1) +#define MS2_P1_8 (1u<<0) +#define MS2_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH2_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH2_PARAMETER_1_LO 62u /* R/W */ +#define MS2_P1_7 (1u<<7) +#define MS2_P1_6 (1u<<6) +#define MS2_P1_5 (1u<<5) +#define MS2_P1_4 (1u<<4) +#define MS2_P1_3 (1u<<3) +#define MS2_P1_2 (1u<<2) +#define MS2_P1_1 (1u<<1) +#define MS2_P1_0 (1u<<0) +#define MS2_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH2_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH2_PARAMETER_3_2_HIHI 63u /* R/W */ +#define MS2_P3_19 (1u<<7) +#define MS2_P3_18 (1u<<6) +#define MS2_P3_17 (1u<<5) +#define MS2_P3_16 (1u<<4) +#define MS2_P3_19_16 (7u<<4) +#define MS2_P2_19 (1u<<3) +#define MS2_P2_18 (1u<<2) +#define MS2_P2_17 (1u<<1) +#define MS2_P2_16 (1u<<0) +#define MS2_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH2_PARAMETER_2_HI 64u /* R/W */ +#define MS2_P2_15 (1u<<7) +#define MS2_P2_14 (1u<<6) +#define MS2_P2_13 (1u<<5) +#define MS2_P2_12 (1u<<4) +#define MS2_P2_11 (1u<<3) +#define MS2_P2_10 (1u<<2) +#define MS2_P2_9 (1u<<1) +#define MS2_P2_8 (1u<<0) +#define MS2_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH2_PARAMETER_2_LO 65u /* R/W */ +#define MS2_P2_7 (1u<<7) +#define MS2_P2_6 (1u<<6) +#define MS2_P2_5 (1u<<5) +#define MS2_P2_4 (1u<<4) +#define MS2_P2_3 (1u<<3) +#define MS2_P2_2 (1u<<2) +#define MS2_P2_1 (1u<<1) +#define MS2_P2_0 (1u<<0) +#define MS2_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH2_PARAMETER_2_LO_RESET_VALUE 0xXX */ + + + + + +/* Multisynth3 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth3 Divider. */ + +#define SI5351_MULTISYNTH3_PARAMETER_3_HI 66u /* R/W */ +#define MS3_P3_15 (1u<<7) +#define MS3_P3_14 (1u<<6) +#define MS3_P3_13 (1u<<5) +#define MS3_P3_12 (1u<<4) +#define MS3_P3_11 (1u<<3) +#define MS3_P3_10 (1u<<2) +#define MS3_P3_9 (1u<<1) +#define MS3_P3_8 (1u<<0) +#define MS3_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH3_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH3_PARAMETER_3_LO 67u /* R/W */ +#define MS3_P3_7 (1u<<7) +#define MS3_P3_6 (1u<<6) +#define MS3_P3_5 (1u<<5) +#define MS3_P3_4 (1u<<4) +#define MS3_P3_3 (1u<<3) +#define MS3_P3_2 (1u<<2) +#define MS3_P3_1 (1u<<1) +#define MS3_P3_0 (1u<<0) +#define MS3_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH3_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth3 Parameters R3 Output Divider, MS3 Divide by 4 Enable, + * Multisynth3 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth3 divider. */ + +#define SI5351_MULTISYNTH3_PARAMETER_DIV 68u /* R/W */ +#define R3_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R3_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R3_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R3_DIV (7u<<4) +#define MS3_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS3_DIVBY4_0 (1u<<2) +#define MS3_DIVBY4 (3u<<2) +#define MS3_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS3_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS3_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH3_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH3_PARAMETER_1_HI 69u /* R/W */ +#define MS3_P1_15 (1u<<7) +#define MS3_P1_14 (1u<<6) +#define MS3_P1_13 (1u<<5) +#define MS3_P1_12 (1u<<4) +#define MS3_P1_11 (1u<<3) +#define MS3_P1_10 (1u<<2) +#define MS3_P1_9 (1u<<1) +#define MS3_P1_8 (1u<<0) +#define MS3_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH3_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH3_PARAMETER_1_LO 70u /* R/W */ +#define MS3_P1_7 (1u<<7) +#define MS3_P1_6 (1u<<6) +#define MS3_P1_5 (1u<<5) +#define MS3_P1_4 (1u<<4) +#define MS3_P1_3 (1u<<3) +#define MS3_P1_2 (1u<<2) +#define MS3_P1_1 (1u<<1) +#define MS3_P1_0 (1u<<0) +#define MS3_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH3_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH3_PARAMETER_3_2_HIHI 71u /* R/W */ +#define MS3_P3_19 (1u<<7) +#define MS3_P3_18 (1u<<6) +#define MS3_P3_17 (1u<<5) +#define MS3_P3_16 (1u<<4) +#define MS3_P3_19_16 (7u<<4) +#define MS3_P2_19 (1u<<3) +#define MS3_P2_18 (1u<<2) +#define MS3_P2_17 (1u<<1) +#define MS3_P2_16 (1u<<0) +#define MS3_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH3_PARAMETER_2_HI 72u /* R/W */ +#define MS3_P2_15 (1u<<7) +#define MS3_P2_14 (1u<<6) +#define MS3_P2_13 (1u<<5) +#define MS3_P2_12 (1u<<4) +#define MS3_P2_11 (1u<<3) +#define MS3_P2_10 (1u<<2) +#define MS3_P2_9 (1u<<1) +#define MS3_P2_8 (1u<<0) +#define MS3_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH3_PARAMETER_2_LO 73u /* R/W */ +#define MS3_P2_7 (1u<<7) +#define MS3_P2_6 (1u<<6) +#define MS3_P2_5 (1u<<5) +#define MS3_P2_4 (1u<<4) +#define MS3_P2_3 (1u<<3) +#define MS3_P2_2 (1u<<2) +#define MS3_P2_1 (1u<<1) +#define MS3_P2_0 (1u<<0) +#define MS3_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH3_PARAMETER_2_LO_RESET_VALUE 0xXX */ + + + + + +/* MULTISYNTH5 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth4 Divider. */ + +#define SI5351_MULTISYNTH4_PARAMETER_3_HI 74u /* R/W */ +#define MS4_P3_15 (1u<<7) +#define MS4_P3_14 (1u<<6) +#define MS4_P3_13 (1u<<5) +#define MS4_P3_12 (1u<<4) +#define MS4_P3_11 (1u<<3) +#define MS4_P3_10 (1u<<2) +#define MS4_P3_9 (1u<<1) +#define MS4_P3_8 (1u<<0) +#define MS4_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH4_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH4_PARAMETER_3_LO 75u /* R/W */ +#define MS4_P3_7 (1u<<7) +#define MS4_P3_6 (1u<<6) +#define MS4_P3_5 (1u<<5) +#define MS4_P3_4 (1u<<4) +#define MS4_P3_3 (1u<<3) +#define MS4_P3_2 (1u<<2) +#define MS4_P3_1 (1u<<1) +#define MS4_P3_0 (1u<<0) +#define MS4_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH4_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth4 Parameters R3 Output Divider, MS4 Divide by 4 Enable, + * Multisynth4 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth3 divider. */ + +#define SI5351_MULTISYNTH4_PARAMETER_DIV 76u /* R/W */ +#define R3_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R3_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R3_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R3_DIV (7u<<4) +#define MS4_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS4_DIVBY4_0 (1u<<2) +#define MS4_DIVBY4 (3u<<2) +#define MS4_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS4_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS4_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH4_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH4_PARAMETER_1_HI 77u /* R/W */ +#define MS4_P1_15 (1u<<7) +#define MS4_P1_14 (1u<<6) +#define MS4_P1_13 (1u<<5) +#define MS4_P1_12 (1u<<4) +#define MS4_P1_11 (1u<<3) +#define MS4_P1_10 (1u<<2) +#define MS4_P1_9 (1u<<1) +#define MS4_P1_8 (1u<<0) +#define MS4_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH4_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH4_PARAMETER_1_LO 78u /* R/W */ +#define MS4_P1_7 (1u<<7) +#define MS4_P1_6 (1u<<6) +#define MS4_P1_5 (1u<<5) +#define MS4_P1_4 (1u<<4) +#define MS4_P1_3 (1u<<3) +#define MS4_P1_2 (1u<<2) +#define MS4_P1_1 (1u<<1) +#define MS4_P1_0 (1u<<0) +#define MS4_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH4_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH4_PARAMETER_3_2_HIHI 79u /* R/W */ +#define MS4_P3_19 (1u<<7) +#define MS4_P3_18 (1u<<6) +#define MS4_P3_17 (1u<<5) +#define MS4_P3_16 (1u<<4) +#define MS4_P3_19_16 (7u<<4) +#define MS4_P2_19 (1u<<3) +#define MS4_P2_18 (1u<<2) +#define MS4_P2_17 (1u<<1) +#define MS4_P2_16 (1u<<0) +#define MS4_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH4_PARAMETER_2_HI 80u /* R/W */ +#define MS4_P2_15 (1u<<7) +#define MS4_P2_14 (1u<<6) +#define MS4_P2_13 (1u<<5) +#define MS4_P2_12 (1u<<4) +#define MS4_P2_11 (1u<<3) +#define MS4_P2_10 (1u<<2) +#define MS4_P2_9 (1u<<1) +#define MS4_P2_8 (1u<<0) +#define MS4_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH4_PARAMETER_2_LO 81u /* R/W */ +#define MS4_P2_7 (1u<<7) +#define MS4_P2_6 (1u<<6) +#define MS4_P2_5 (1u<<5) +#define MS4_P2_4 (1u<<4) +#define MS4_P2_3 (1u<<3) +#define MS4_P2_2 (1u<<2) +#define MS4_P2_1 (1u<<1) +#define MS4_P2_0 (1u<<0) +#define MS4_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH4_PARAMETER_2_LO_RESET_VALUE 0xXX */ + + + + + + + + + +/* Multisynth5 Parameter 3. +This 20-bit number is an encoded representation of the denominator for the frac- +tional part of the MultiSynth5 Divider. */ + +#define SI5351_MULTISYNTH5_PARAMETER_3_HI 82u /* R/W */ +#define MS5_P3_15 (1u<<7) +#define MS5_P3_14 (1u<<6) +#define MS5_P3_13 (1u<<5) +#define MS5_P3_12 (1u<<4) +#define MS5_P3_11 (1u<<3) +#define MS5_P3_10 (1u<<2) +#define MS5_P3_9 (1u<<1) +#define MS5_P3_8 (1u<<0) +#define MS5_P3_15_8 (0xFF) +/* #define SI5351_MULTISYNTH5_PARAMETER_3_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH5_PARAMETER_3_LO 83u /* R/W */ +#define MS5_P3_7 (1u<<7) +#define MS5_P3_6 (1u<<6) +#define MS5_P3_5 (1u<<5) +#define MS5_P3_4 (1u<<4) +#define MS5_P3_3 (1u<<3) +#define MS5_P3_2 (1u<<2) +#define MS5_P3_1 (1u<<1) +#define MS5_P3_0 (1u<<0) +#define MS5_P3_7_0 (0xFF) +/* #define SI5351_MULTISYNTH5_PARAMETER_3_LO_RESET_VALUE 0xXX */ + +/* Multisynth5 Parameters R3 Output Divider, MS5 Divide by 4 Enable, + * Multisynth5 Parameter 1 +This 18-bit number is an encoded representation of the integer part of the Multi- +Synth3 divider. */ + +#define SI5351_MULTISYNTH5_PARAMETER_DIV 84u /* R/W */ +#define R3_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R3_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R3_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R3_DIV (7u<<4) +#define MS5_DIVBY4_1 (1u<<3) /* 11: Divide by 4 enabled, 00: Divide by a value other than 4 */ +#define MS5_DIVBY4_0 (1u<<2) +#define MS5_DIVBY4 (3u<<2) +#define MS5_P1_17 (1u<<1) /* Multisynth0 Parameter 1, This 18-bit number is an encoded representation */ +#define MS5_P1_16 (1u<<0) /* of the integer part of the Multisynth0 divider */ +#define MS5_P1_17_16 (3u<<0) +/* #define SI5351_MULTISYNTH5_PARAMETER_DIV_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH5_PARAMETER_1_HI 85u /* R/W */ +#define MS5_P1_15 (1u<<7) +#define MS5_P1_14 (1u<<6) +#define MS5_P1_13 (1u<<5) +#define MS5_P1_12 (1u<<4) +#define MS5_P1_11 (1u<<3) +#define MS5_P1_10 (1u<<2) +#define MS5_P1_9 (1u<<1) +#define MS5_P1_8 (1u<<0) +#define MS5_P1_15_8 (0xFF) +/* #define SI5351_MULTISYNTH5_PARAMETER_1_HI_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH5_PARAMETER_1_LO 86u /* R/W */ +#define MS5_P1_7 (1u<<7) +#define MS5_P1_6 (1u<<6) +#define MS5_P1_5 (1u<<5) +#define MS5_P1_4 (1u<<4) +#define MS5_P1_3 (1u<<3) +#define MS5_P1_2 (1u<<2) +#define MS5_P1_1 (1u<<1) +#define MS5_P1_0 (1u<<0) +#define MS5_P1_7_0 (0xFF) +/* #define SI5351_MULTISYNTH5_PARAMETER_1_LO_RESET_VALUE 0xXX */ + +#define SI5351_MULTISYNTH5_PARAMETER_3_2_HIHI 87u /* R/W */ +#define MS5_P3_19 (1u<<7) +#define MS5_P3_18 (1u<<6) +#define MS5_P3_17 (1u<<5) +#define MS5_P3_16 (1u<<4) +#define MS5_P3_19_16 (7u<<4) +#define MS5_P2_19 (1u<<3) +#define MS5_P2_18 (1u<<2) +#define MS5_P2_17 (1u<<1) +#define MS5_P2_16 (1u<<0) +#define MS5_P2_19_16 (7u<<0) + +#define SI5351_MULTISYNTH5_PARAMETER_2_HI 88u /* R/W */ +#define MS5_P2_15 (1u<<7) +#define MS5_P2_14 (1u<<6) +#define MS5_P2_13 (1u<<5) +#define MS5_P2_12 (1u<<4) +#define MS5_P2_11 (1u<<3) +#define MS5_P2_10 (1u<<2) +#define MS5_P2_9 (1u<<1) +#define MS5_P2_8 (1u<<0) +#define MS5_P2_15_8 (0xFF) + +#define SI5351_MULTISYNTH5_PARAMETER_2_LO 89u /* R/W */ +#define MS5_P2_7 (1u<<7) +#define MS5_P2_6 (1u<<6) +#define MS5_P2_5 (1u<<5) +#define MS5_P2_4 (1u<<4) +#define MS5_P2_3 (1u<<3) +#define MS5_P2_2 (1u<<2) +#define MS5_P2_1 (1u<<1) +#define MS5_P2_0 (1u<<0) +#define MS5_P2_7_0 (0xFF) +/* #define SI5351_MULTISYNTH5_PARAMETER_2_LO_RESET_VALUE 0xXX */ + + +/* Multisynth6 Parameter 1. +This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be +even integers greater than or equal to 6. All other divide values are invalid. */ + +#define SI5351_MULTISYNTH6_PARAMETER_1 90u /* R/W */ +#define MS6_P1_7 (1u<<7) +#define MS6_P1_6 (1u<<6) +#define MS6_P1_5 (1u<<5) +#define MS6_P1_4 (1u<<4) +#define MS6_P1_3 (1u<<3) +#define MS6_P1_2 (1u<<2) +#define MS6_P1_1 (1u<<1) +#define MS6_P1_0 (1u<<0) +#define MS6_P1 (0xFF) +/* #define SI5351_MULTISYNTH6_PARAMETER_1_RESET_VALUE 0xXX */ + + +/* Multisynth7 Parameter 1. +This 8-bit number is the Multisynth7 divide ratio. Multisynth7 divide ratio can only be +even integers greater than or equal to 6. All other divide values are invalid. */ + +#define SI5351_MULTISYNTH7_PARAMETER_1 91u /* R/W */ +#define MS7_P1_7 (1u<<7) +#define MS7_P1_6 (1u<<6) +#define MS7_P1_5 (1u<<5) +#define MS7_P1_4 (1u<<4) +#define MS7_P1_3 (1u<<3) +#define MS7_P1_2 (1u<<2) +#define MS7_P1_1 (1u<<1) +#define MS7_P1_0 (1u<<0) +#define MS7_P1 (0xFF) +/* #define SI5351_MULTISYNTH7_PARAMETER_1_RESET_VALUE 0xXX */ + +#define SI5351_CLOCK_6_7_OUTPUT_DEVIDER 92u /* R/W */ +#define R7_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R7_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R7_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R7_DIV (7u<<4) +#define R6_DIV_2 (1u<<6) /* 000b: Divide by 1, 001b: Divide by 2, 010b: Divide by 4, */ +#define R6_DIV_1 (1u<<5) /* 011b: Divide by 8, 100b: Divide by 16, 101b: Divide by 32, */ +#define R6_DIV_0 (1u<<4) /* 110b: Divide by 64, 111b: Divide by 128 */ +#define R6_DIV (7u<<4) + + diff --git a/Core/Src/main.c b/Core/Src/main.c index 4528729..ed71520 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -101,7 +101,7 @@ void start_id_task(void *argument); int main(void) { /* USER CODE BEGIN 1 */ - + int status = 0; /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ @@ -142,6 +142,10 @@ int main(void) printf("Device No. %d (Instance No: 0x%x) is %s\n", i, (unsigned int) instance_si5351[i], (ready==0) ? "ready" : "N/A"); } + + status = si5351_program(instance_si5351[1]); + printf("Device #1 gets status %d\n", status); + for (int i=2; i>=0; i--) { si5351_deinit(instance_si5351[i]); } diff --git a/Core/Src/stm32_si5351.c b/Core/Src/stm32_si5351.c index 55c3c1b..6d28b6c 100644 --- a/Core/Src/stm32_si5351.c +++ b/Core/Src/stm32_si5351.c @@ -23,12 +23,12 @@ */ typedef struct __SI5351_HandleTypeDef { void * i2c_handle; - - uint32_t xtal_frequency; + uint32_t xtal_frequency; /*!< XTAL or CLKIN frequency */ int si5351_num; struct __SI5351_HandleTypeDef *next; - uint8_t i2c_address; - uint8_t initialized:1; + uint8_t i2c_address; /*!< I2C address of the datasheet */ + // uint8_t interrupt_status_mask; /*!< Reg 2: Interrupt Status Mask */ + uint8_t initialized:1; /*!< mark the driver initialized */ } si5351_HandleTypeDef; /* Private define ------------------------------------------------------------*/ @@ -39,6 +39,34 @@ int si5351_errno = 0; /* error_number for functions whith return == NULL */ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* wrapper function for receiving bytes from I2C bus + */ + +static int si5351_error_status_i2c(HAL_StatusTypeDef status) { + switch (status) { + case HAL_TIMEOUT: return -ETIMEDOUT; break; + case HAL_ERROR: return -EIO; break; + case HAL_BUSY: return -EBUSY; break; + default: return 0; + } +} + +int si5351_read(si5351_inst_t instance, uint8_t regaddr, uint8_t *data, uint16_t size) { + + HAL_StatusTypeDef status; + status = HAL_I2C_Mem_Read(instance->i2c_handle, instance->i2c_address<<1, + (uint16_t)regaddr, I2C_MEMADD_SIZE_8BIT, data, size, 0xffff); + return si5351_error_status_i2c(status); +} + +int si5351_write(si5351_inst_t instance, uint8_t regaddr, uint8_t *data, uint16_t size) { + + HAL_StatusTypeDef status; + status = HAL_I2C_Mem_Write(instance->i2c_handle, instance->i2c_address<<1, + (uint16_t)regaddr, I2C_MEMADD_SIZE_8BIT, data, size, 0xffff); + return si5351_error_status_i2c(status); +} + /** @brief Initialize the device Si5351 with the main parameters * @param i2c_handle the handle of the I2C bus from HAL function, e.g. hi2c1 * @param xtal_frequency either the XTAL frequency (25/27 MHz) or CLock-In @@ -56,10 +84,6 @@ si5351_HandleTypeDef *si5351_init(void * i2c_handle, uint32_t xtal_frequency, ui return NULL; } -#ifdef HAL_I2C_MODULE_ENABLED - -#endif - si5351_handle = calloc(1, sizeof(*si5351_handle)); if (si5351_handle == NULL) { si5351_errno = ENOMEM; // cannot allocate any memory @@ -125,7 +149,7 @@ int si5351_deinit(si5351_HandleTypeDef * si5351_handle) { return 0; } -/** @brief Check if there is the I2C device ready on the bus +/** @brief Check if there is any I2C device ready on the bus * @param si5351_instance Given si5351 device handle * @return 0 on success (HAL_StatusTypeDef) * @retval HAL_ERROR = 0x01 @@ -144,6 +168,42 @@ int si5351_isready(si5351_inst_t inst) { /* @TODO: create a pointer to that function for more flexiblity using other tools as HAL */ return status; } + +int si5351_program(si5351_inst_t inst) { + + uint8_t data; + int status = 0; + + if(!inst) + return -EINVAL; + + do { + status = si5351_read(inst, SI5351_DEVICE_STATUS, &data, 1); + if (status) + return status; + + } while(data & SI5351_SYS_INIT); + + /* Disable Outputs Set CLKx_DIS high, Reg. 3 = 0xFF */ + data = 0xff; + status = si5351_write(inst, SI5351_OUTPUT_ENABLE_CONTROL, &data, 1); + if (status) + return status; + + /* power down all output drivers reg 16 -- 23 */ + data = 0x80; + for(int i = SI5351_CLK0_CONTROL; i <= SI5351_CLK7_CONTROL; i++) { + status = si5351_write(inst, i, &data, 1); + if (status) + return status; + } + + + + + return 0; +} + #if 0