UPD CMSIS/Include to V5.6
Dieser Commit ist enthalten in:
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/******************************************************************************
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* @file cachel1_armv7.h
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* @brief CMSIS Level 1 Cache API for Armv7-M and later
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* @version V1.0.1
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* @date 19. April 2021
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******************************************************************************/
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/*
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* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef ARM_CACHEL1_ARMV7_H
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#define ARM_CACHEL1_ARMV7_H
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/**
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\ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_CacheFunctions Cache Functions
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\brief Functions that configure Instruction and Data cache.
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@{
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*/
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/* Cache Size ID Register Macros */
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#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
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#ifndef __SCB_DCACHE_LINE_SIZE
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#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
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#endif
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#ifndef __SCB_ICACHE_LINE_SIZE
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#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
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#endif
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/**
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\brief Enable I-Cache
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\details Turns on I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_EnableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
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__DSB();
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__ISB();
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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__DSB();
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__ISB();
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SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Disable I-Cache
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\details Turns off I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_DisableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__ISB();
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SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Invalidate I-Cache
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\details Invalidates I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__ISB();
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SCB->ICIALLU = 0UL;
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief I-Cache Invalidate by address
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\details Invalidates I-Cache for the given address.
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I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
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I-Cache memory blocks which are part of given address + given size are invalidated.
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\param[in] addr address
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\param[in] isize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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if ( isize > 0 ) {
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int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
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__DSB();
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do {
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SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
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op_addr += __SCB_ICACHE_LINE_SIZE;
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op_size -= __SCB_ICACHE_LINE_SIZE;
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} while ( op_size > 0 );
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__DSB();
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__ISB();
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}
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#endif
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}
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/**
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\brief Enable D-Cache
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\details Turns on D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_EnableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
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((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Disable D-Cache
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\details Turns off D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_DisableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean & invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Invalidate D-Cache
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\details Invalidates D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
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((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Clean D-Cache
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\details Cleans D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_CleanDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
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((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Clean & Invalidate D-Cache
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\details Cleans and Invalidates D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean & invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief D-Cache Invalidate by address
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\details Invalidates D-Cache for the given address.
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D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
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D-Cache memory blocks which are part of given address + given size are invalidated.
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\param[in] addr address
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\param[in] dsize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if ( dsize > 0 ) {
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int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
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__DSB();
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do {
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SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
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op_addr += __SCB_DCACHE_LINE_SIZE;
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op_size -= __SCB_DCACHE_LINE_SIZE;
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} while ( op_size > 0 );
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__DSB();
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__ISB();
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}
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#endif
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}
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/**
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\brief D-Cache Clean by address
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\details Cleans D-Cache for the given address
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D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
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D-Cache memory blocks which are part of given address + given size are cleaned.
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\param[in] addr address
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\param[in] dsize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if ( dsize > 0 ) {
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int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
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__DSB();
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do {
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SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
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op_addr += __SCB_DCACHE_LINE_SIZE;
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op_size -= __SCB_DCACHE_LINE_SIZE;
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} while ( op_size > 0 );
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||||||
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__DSB();
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__ISB();
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||||||
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}
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||||||
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#endif
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||||||
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}
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||||||
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||||||
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||||||
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/**
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\brief D-Cache Clean and Invalidate by address
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||||||
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\details Cleans and invalidates D_Cache for the given address
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||||||
|
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||||
|
\param[in] addr address (aligned to 32-byte boundary)
|
||||||
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
if ( dsize > 0 ) {
|
||||||
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
do {
|
||||||
|
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_CacheFunctions */
|
||||||
|
|
||||||
|
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||||
Datei-Diff unterdrückt, da er zu groß ist
Diff laden
+1503
-1444
Datei-Diff unterdrückt, da er zu groß ist
Diff laden
Datei-Diff unterdrückt, da er zu groß ist
Diff laden
@@ -1,283 +1,283 @@
|
|||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_compiler.h
|
* @file cmsis_compiler.h
|
||||||
* @brief CMSIS compiler generic header file
|
* @brief CMSIS compiler generic header file
|
||||||
* @version V5.1.0
|
* @version V5.1.0
|
||||||
* @date 09. October 2018
|
* @date 09. October 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
* not use this file except in compliance with the License.
|
* not use this file except in compliance with the License.
|
||||||
* You may obtain a copy of the License at
|
* You may obtain a copy of the License at
|
||||||
*
|
*
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
*
|
*
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __CMSIS_COMPILER_H
|
#ifndef __CMSIS_COMPILER_H
|
||||||
#define __CMSIS_COMPILER_H
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Arm Compiler 4/5
|
* Arm Compiler 4/5
|
||||||
*/
|
*/
|
||||||
#if defined ( __CC_ARM )
|
#if defined ( __CC_ARM )
|
||||||
#include "cmsis_armcc.h"
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Arm Compiler 6.6 LTM (armclang)
|
* Arm Compiler 6.6 LTM (armclang)
|
||||||
*/
|
*/
|
||||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||||
#include "cmsis_armclang_ltm.h"
|
#include "cmsis_armclang_ltm.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Arm Compiler above 6.10.1 (armclang)
|
* Arm Compiler above 6.10.1 (armclang)
|
||||||
*/
|
*/
|
||||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||||
#include "cmsis_armclang.h"
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* GNU Compiler
|
* GNU Compiler
|
||||||
*/
|
*/
|
||||||
#elif defined ( __GNUC__ )
|
#elif defined ( __GNUC__ )
|
||||||
#include "cmsis_gcc.h"
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* IAR Compiler
|
* IAR Compiler
|
||||||
*/
|
*/
|
||||||
#elif defined ( __ICCARM__ )
|
#elif defined ( __ICCARM__ )
|
||||||
#include <cmsis_iccarm.h>
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TI Arm Compiler
|
* TI Arm Compiler
|
||||||
*/
|
*/
|
||||||
#elif defined ( __TI_ARM__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#include <cmsis_ccs.h>
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
#ifndef __ASM
|
#ifndef __ASM
|
||||||
#define __ASM __asm
|
#define __ASM __asm
|
||||||
#endif
|
#endif
|
||||||
#ifndef __INLINE
|
#ifndef __INLINE
|
||||||
#define __INLINE inline
|
#define __INLINE inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_INLINE
|
#ifndef __STATIC_INLINE
|
||||||
#define __STATIC_INLINE static inline
|
#define __STATIC_INLINE static inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_FORCEINLINE
|
#ifndef __STATIC_FORCEINLINE
|
||||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
#endif
|
#endif
|
||||||
#ifndef __NO_RETURN
|
#ifndef __NO_RETURN
|
||||||
#define __NO_RETURN __attribute__((noreturn))
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __USED
|
#ifndef __USED
|
||||||
#define __USED __attribute__((used))
|
#define __USED __attribute__((used))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __WEAK
|
#ifndef __WEAK
|
||||||
#define __WEAK __attribute__((weak))
|
#define __WEAK __attribute__((weak))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED
|
#ifndef __PACKED
|
||||||
#define __PACKED __attribute__((packed))
|
#define __PACKED __attribute__((packed))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_STRUCT
|
#ifndef __PACKED_STRUCT
|
||||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_UNION
|
#ifndef __PACKED_UNION
|
||||||
#define __PACKED_UNION union __attribute__((packed))
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_WRITE
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_READ
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_WRITE
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_READ
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __ALIGNED
|
#ifndef __ALIGNED
|
||||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __RESTRICT
|
#ifndef __RESTRICT
|
||||||
#define __RESTRICT __restrict
|
#define __RESTRICT __restrict
|
||||||
#endif
|
#endif
|
||||||
#ifndef __COMPILER_BARRIER
|
#ifndef __COMPILER_BARRIER
|
||||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
#define __COMPILER_BARRIER() (void)0
|
#define __COMPILER_BARRIER() (void)0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TASKING Compiler
|
* TASKING Compiler
|
||||||
*/
|
*/
|
||||||
#elif defined ( __TASKING__ )
|
#elif defined ( __TASKING__ )
|
||||||
/*
|
/*
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
* Including the CMSIS ones.
|
* Including the CMSIS ones.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ASM
|
#ifndef __ASM
|
||||||
#define __ASM __asm
|
#define __ASM __asm
|
||||||
#endif
|
#endif
|
||||||
#ifndef __INLINE
|
#ifndef __INLINE
|
||||||
#define __INLINE inline
|
#define __INLINE inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_INLINE
|
#ifndef __STATIC_INLINE
|
||||||
#define __STATIC_INLINE static inline
|
#define __STATIC_INLINE static inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_FORCEINLINE
|
#ifndef __STATIC_FORCEINLINE
|
||||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
#endif
|
#endif
|
||||||
#ifndef __NO_RETURN
|
#ifndef __NO_RETURN
|
||||||
#define __NO_RETURN __attribute__((noreturn))
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __USED
|
#ifndef __USED
|
||||||
#define __USED __attribute__((used))
|
#define __USED __attribute__((used))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __WEAK
|
#ifndef __WEAK
|
||||||
#define __WEAK __attribute__((weak))
|
#define __WEAK __attribute__((weak))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED
|
#ifndef __PACKED
|
||||||
#define __PACKED __packed__
|
#define __PACKED __packed__
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_STRUCT
|
#ifndef __PACKED_STRUCT
|
||||||
#define __PACKED_STRUCT struct __packed__
|
#define __PACKED_STRUCT struct __packed__
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_UNION
|
#ifndef __PACKED_UNION
|
||||||
#define __PACKED_UNION union __packed__
|
#define __PACKED_UNION union __packed__
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
struct __packed__ T_UINT32 { uint32_t v; };
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_WRITE
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_READ
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_WRITE
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_READ
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __ALIGNED
|
#ifndef __ALIGNED
|
||||||
#define __ALIGNED(x) __align(x)
|
#define __ALIGNED(x) __align(x)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __RESTRICT
|
#ifndef __RESTRICT
|
||||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
#define __RESTRICT
|
#define __RESTRICT
|
||||||
#endif
|
#endif
|
||||||
#ifndef __COMPILER_BARRIER
|
#ifndef __COMPILER_BARRIER
|
||||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
#define __COMPILER_BARRIER() (void)0
|
#define __COMPILER_BARRIER() (void)0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* COSMIC Compiler
|
* COSMIC Compiler
|
||||||
*/
|
*/
|
||||||
#elif defined ( __CSMC__ )
|
#elif defined ( __CSMC__ )
|
||||||
#include <cmsis_csm.h>
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
#ifndef __ASM
|
#ifndef __ASM
|
||||||
#define __ASM _asm
|
#define __ASM _asm
|
||||||
#endif
|
#endif
|
||||||
#ifndef __INLINE
|
#ifndef __INLINE
|
||||||
#define __INLINE inline
|
#define __INLINE inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_INLINE
|
#ifndef __STATIC_INLINE
|
||||||
#define __STATIC_INLINE static inline
|
#define __STATIC_INLINE static inline
|
||||||
#endif
|
#endif
|
||||||
#ifndef __STATIC_FORCEINLINE
|
#ifndef __STATIC_FORCEINLINE
|
||||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
#endif
|
#endif
|
||||||
#ifndef __NO_RETURN
|
#ifndef __NO_RETURN
|
||||||
// NO RETURN is automatically detected hence no warning here
|
// NO RETURN is automatically detected hence no warning here
|
||||||
#define __NO_RETURN
|
#define __NO_RETURN
|
||||||
#endif
|
#endif
|
||||||
#ifndef __USED
|
#ifndef __USED
|
||||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
#define __USED
|
#define __USED
|
||||||
#endif
|
#endif
|
||||||
#ifndef __WEAK
|
#ifndef __WEAK
|
||||||
#define __WEAK __weak
|
#define __WEAK __weak
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED
|
#ifndef __PACKED
|
||||||
#define __PACKED @packed
|
#define __PACKED @packed
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_STRUCT
|
#ifndef __PACKED_STRUCT
|
||||||
#define __PACKED_STRUCT @packed struct
|
#define __PACKED_STRUCT @packed struct
|
||||||
#endif
|
#endif
|
||||||
#ifndef __PACKED_UNION
|
#ifndef __PACKED_UNION
|
||||||
#define __PACKED_UNION @packed union
|
#define __PACKED_UNION @packed union
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
@packed struct T_UINT32 { uint32_t v; };
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_WRITE
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT16_READ
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_WRITE
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
#endif
|
#endif
|
||||||
#ifndef __UNALIGNED_UINT32_READ
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __ALIGNED
|
#ifndef __ALIGNED
|
||||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
#define __ALIGNED(x)
|
#define __ALIGNED(x)
|
||||||
#endif
|
#endif
|
||||||
#ifndef __RESTRICT
|
#ifndef __RESTRICT
|
||||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
#define __RESTRICT
|
#define __RESTRICT
|
||||||
#endif
|
#endif
|
||||||
#ifndef __COMPILER_BARRIER
|
#ifndef __COMPILER_BARRIER
|
||||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
#define __COMPILER_BARRIER() (void)0
|
#define __COMPILER_BARRIER() (void)0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#error Unknown compiler.
|
#error Unknown compiler.
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#endif /* __CMSIS_COMPILER_H */
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
||||||
|
|||||||
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|
|||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_version.h
|
* @file cmsis_version.h
|
||||||
* @brief CMSIS Core(M) Version definitions
|
* @brief CMSIS Core(M) Version definitions
|
||||||
* @version V5.0.3
|
* @version V5.0.5
|
||||||
* @date 24. June 2019
|
* @date 02. February 2022
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
* not use this file except in compliance with the License.
|
* not use this file except in compliance with the License.
|
||||||
* You may obtain a copy of the License at
|
* You may obtain a copy of the License at
|
||||||
*
|
*
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
*
|
*
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined (__clang__)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __CMSIS_VERSION_H
|
#ifndef __CMSIS_VERSION_H
|
||||||
#define __CMSIS_VERSION_H
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
/* CMSIS Version definitions */
|
/* CMSIS Version definitions */
|
||||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
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|
|||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
* @file mpu_armv7.h
|
* @file mpu_armv7.h
|
||||||
* @brief CMSIS MPU API for Armv7-M MPU
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
* @version V5.1.0
|
* @version V5.1.2
|
||||||
* @date 08. March 2019
|
* @date 25. May 2020
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
* not use this file except in compliance with the License.
|
* not use this file except in compliance with the License.
|
||||||
* You may obtain a copy of the License at
|
* You may obtain a copy of the License at
|
||||||
*
|
*
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
*
|
*
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined (__clang__)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef ARM_MPU_ARMV7_H
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
#define ARM_MPU_ARMV7_H
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
/** MPU Region Base Address Register Value
|
/** MPU Region Base Address Register Value
|
||||||
*
|
*
|
||||||
* \param Region The region to be configured, number 0 to 15.
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
* \param BaseAddress The base address for the region.
|
* \param BaseAddress The base address for the region.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
(MPU_RBAR_VALID_Msk))
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attributes
|
* MPU Memory Access Attributes
|
||||||
*
|
*
|
||||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
* \param IsShareable Region is shareable between multiple bus masters.
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Region Attribute and Size Register Value
|
* MPU Region Attribute and Size Register Value
|
||||||
*
|
*
|
||||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
* \param SubRegionDisable Sub-region disable field.
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||||
(((MPU_RASR_ENABLE_Msk))))
|
(((MPU_RASR_ENABLE_Msk))))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Region Attribute and Size Register Value
|
* MPU Region Attribute and Size Register Value
|
||||||
*
|
*
|
||||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
* \param IsShareable Region is shareable between multiple bus masters.
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
* \param SubRegionDisable Sub-region disable field.
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute for strongly ordered memory.
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
* - TEX: 000b
|
* - TEX: 000b
|
||||||
* - Shareable
|
* - Shareable
|
||||||
* - Non-cacheable
|
* - Non-cacheable
|
||||||
* - Non-bufferable
|
* - Non-bufferable
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute for device memory.
|
* MPU Memory Access Attribute for device memory.
|
||||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||||
* - Shareable or non-shareable
|
* - Shareable or non-shareable
|
||||||
* - Non-cacheable
|
* - Non-cacheable
|
||||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
*
|
*
|
||||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute for normal memory.
|
* MPU Memory Access Attribute for normal memory.
|
||||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
* - Shareable or non-shareable
|
* - Shareable or non-shareable
|
||||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
*
|
*
|
||||||
* \param OuterCp Configures the outer cache policy.
|
* \param OuterCp Configures the outer cache policy.
|
||||||
* \param InnerCp Configures the inner cache policy.
|
* \param InnerCp Configures the inner cache policy.
|
||||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute non-cacheable policy.
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Struct for a single MPU Region
|
* Struct for a single MPU Region
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
} ARM_MPU_Region_t;
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
/** Enable the MPU.
|
/** Enable the MPU.
|
||||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
{
|
{
|
||||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
__DMB();
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
#endif
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
__DSB();
|
#endif
|
||||||
__ISB();
|
__DSB();
|
||||||
}
|
__ISB();
|
||||||
|
}
|
||||||
/** Disable the MPU.
|
|
||||||
*/
|
/** Disable the MPU.
|
||||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
*/
|
||||||
{
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
__DMB();
|
{
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
__DMB();
|
||||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
#endif
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
#endif
|
||||||
}
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
__DSB();
|
||||||
/** Clear and disable the given MPU region.
|
__ISB();
|
||||||
* \param rnr Region number to be cleared.
|
}
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
/** Clear and disable the given MPU region.
|
||||||
{
|
* \param rnr Region number to be cleared.
|
||||||
MPU->RNR = rnr;
|
*/
|
||||||
MPU->RASR = 0U;
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
}
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
/** Configure an MPU region.
|
MPU->RASR = 0U;
|
||||||
* \param rbar Value for RBAR register.
|
}
|
||||||
* \param rsar Value for RSAR register.
|
|
||||||
*/
|
/** Configure an MPU region.
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
* \param rbar Value for RBAR register.
|
||||||
{
|
* \param rasr Value for RASR register.
|
||||||
MPU->RBAR = rbar;
|
*/
|
||||||
MPU->RASR = rasr;
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
}
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
/** Configure the given MPU region.
|
MPU->RASR = rasr;
|
||||||
* \param rnr Region number to be configured.
|
}
|
||||||
* \param rbar Value for RBAR register.
|
|
||||||
* \param rsar Value for RSAR register.
|
/** Configure the given MPU region.
|
||||||
*/
|
* \param rnr Region number to be configured.
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
* \param rbar Value for RBAR register.
|
||||||
{
|
* \param rasr Value for RASR register.
|
||||||
MPU->RNR = rnr;
|
*/
|
||||||
MPU->RBAR = rbar;
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
MPU->RASR = rasr;
|
{
|
||||||
}
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
MPU->RASR = rasr;
|
||||||
* \param dst Destination data is copied to.
|
}
|
||||||
* \param src Source data is copied from.
|
|
||||||
* \param len Amount of data words to be copied.
|
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||||
*/
|
* \param dst Destination data is copied to.
|
||||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
* \param src Source data is copied from.
|
||||||
{
|
* \param len Amount of data words to be copied.
|
||||||
uint32_t i;
|
*/
|
||||||
for (i = 0U; i < len; ++i)
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
{
|
{
|
||||||
dst[i] = src[i];
|
uint32_t i;
|
||||||
}
|
for (i = 0U; i < len; ++i)
|
||||||
}
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
/** Load the given number of MPU regions from a table.
|
}
|
||||||
* \param table Pointer to the MPU configuration table.
|
}
|
||||||
* \param cnt Amount of regions to be configured.
|
|
||||||
*/
|
/** Load the given number of MPU regions from a table.
|
||||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
* \param table Pointer to the MPU configuration table.
|
||||||
{
|
* \param cnt Amount of regions to be configured.
|
||||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
*/
|
||||||
while (cnt > MPU_TYPE_RALIASES) {
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
{
|
||||||
table += MPU_TYPE_RALIASES;
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
cnt -= MPU_TYPE_RALIASES;
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
}
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
table += MPU_TYPE_RALIASES;
|
||||||
}
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
#endif
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|||||||
@@ -1,346 +1,352 @@
|
|||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
* @file mpu_armv8.h
|
* @file mpu_armv8.h
|
||||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||||
* @version V5.1.0
|
* @version V5.1.3
|
||||||
* @date 08. March 2019
|
* @date 03. February 2021
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
* not use this file except in compliance with the License.
|
* not use this file except in compliance with the License.
|
||||||
* You may obtain a copy of the License at
|
* You may obtain a copy of the License at
|
||||||
*
|
*
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
*
|
*
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined (__clang__)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef ARM_MPU_ARMV8_H
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
#define ARM_MPU_ARMV8_H
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
/** \brief Attribute for device memory (outer only) */
|
/** \brief Attribute for device memory (outer only) */
|
||||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
/** \brief Attribute for non-cacheable, normal memory */
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
/** \brief Attribute for normal memory (outer and inner)
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||||
|
|
||||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
/** \brief Memory Attribute
|
/** \brief Memory Attribute
|
||||||
* \param O Outer memory attributes
|
* \param O Outer memory attributes
|
||||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||||
|
|
||||||
/** \brief Normal memory non-shareable */
|
/** \brief Normal memory non-shareable */
|
||||||
#define ARM_MPU_SH_NON (0U)
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
/** \brief Normal memory outer shareable */
|
/** \brief Normal memory outer shareable */
|
||||||
#define ARM_MPU_SH_OUTER (2U)
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
/** \brief Normal memory inner shareable */
|
/** \brief Normal memory inner shareable */
|
||||||
#define ARM_MPU_SH_INNER (3U)
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
/** \brief Memory access permissions
|
/** \brief Memory access permissions
|
||||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||||
|
|
||||||
/** \brief Region Base Address Register value
|
/** \brief Region Base Address Register value
|
||||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
* \param SH Defines the Shareability domain for this memory region.
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
/** \brief Region Limit Address Register value
|
/** \brief Region Limit Address Register value
|
||||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
* \param IDX The attribute index to be associated with this memory region.
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
(MPU_RLAR_EN_Msk))
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
#if defined(MPU_RLAR_PXN_Pos)
|
#if defined(MPU_RLAR_PXN_Pos)
|
||||||
|
|
||||||
/** \brief Region Limit Address Register with PXN value
|
/** \brief Region Limit Address Register with PXN value
|
||||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||||
* \param IDX The attribute index to be associated with this memory region.
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
*/
|
*/
|
||||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
(MPU_RLAR_EN_Msk))
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Struct for a single MPU Region
|
* Struct for a single MPU Region
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
} ARM_MPU_Region_t;
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
/** Enable the MPU.
|
/** Enable the MPU.
|
||||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
{
|
{
|
||||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
__DMB();
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
#endif
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
__DSB();
|
#endif
|
||||||
__ISB();
|
__DSB();
|
||||||
}
|
__ISB();
|
||||||
|
}
|
||||||
/** Disable the MPU.
|
|
||||||
*/
|
/** Disable the MPU.
|
||||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
*/
|
||||||
{
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
__DMB();
|
{
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
__DMB();
|
||||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
#endif
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
#endif
|
||||||
}
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
__DSB();
|
||||||
#ifdef MPU_NS
|
__ISB();
|
||||||
/** Enable the Non-secure MPU.
|
}
|
||||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
|
||||||
*/
|
#ifdef MPU_NS
|
||||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
/** Enable the Non-secure MPU.
|
||||||
{
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
*/
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
{
|
||||||
#endif
|
__DMB();
|
||||||
__DSB();
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
__ISB();
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
}
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
/** Disable the Non-secure MPU.
|
__DSB();
|
||||||
*/
|
__ISB();
|
||||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
}
|
||||||
{
|
|
||||||
__DMB();
|
/** Disable the Non-secure MPU.
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
*/
|
||||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
#endif
|
{
|
||||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
__DMB();
|
||||||
}
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
#endif
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
/** Set the memory attribute encoding to the given MPU.
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
* \param mpu Pointer to the MPU to be configured.
|
__DSB();
|
||||||
* \param idx The attribute index to be set [0-7]
|
__ISB();
|
||||||
* \param attr The attribute value to be set.
|
}
|
||||||
*/
|
#endif
|
||||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
|
||||||
{
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
const uint8_t reg = idx / 4U;
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
const uint32_t pos = ((idx % 4U) * 8U);
|
* \param idx The attribute index to be set [0-7]
|
||||||
const uint32_t mask = 0xFFU << pos;
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
return; // invalid index
|
{
|
||||||
}
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
const uint32_t mask = 0xFFU << pos;
|
||||||
}
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
/** Set the memory attribute encoding.
|
return; // invalid index
|
||||||
* \param idx The attribute index to be set [0-7]
|
}
|
||||||
* \param attr The attribute value to be set.
|
|
||||||
*/
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
}
|
||||||
{
|
|
||||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
/** Set the memory attribute encoding.
|
||||||
}
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
#ifdef MPU_NS
|
*/
|
||||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
* \param idx The attribute index to be set [0-7]
|
{
|
||||||
* \param attr The attribute value to be set.
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
*/
|
}
|
||||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
|
||||||
{
|
#ifdef MPU_NS
|
||||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
}
|
* \param idx The attribute index to be set [0-7]
|
||||||
#endif
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
/** Clear and disable the given MPU region of the given MPU.
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
* \param mpu Pointer to MPU to be used.
|
{
|
||||||
* \param rnr Region number to be cleared.
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
*/
|
}
|
||||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
#endif
|
||||||
{
|
|
||||||
mpu->RNR = rnr;
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
mpu->RLAR = 0U;
|
* \param mpu Pointer to MPU to be used.
|
||||||
}
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
/** Clear and disable the given MPU region.
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
* \param rnr Region number to be cleared.
|
{
|
||||||
*/
|
mpu->RNR = rnr;
|
||||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
mpu->RLAR = 0U;
|
||||||
{
|
}
|
||||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
|
||||||
}
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
#ifdef MPU_NS
|
*/
|
||||||
/** Clear and disable the given Non-secure MPU region.
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
* \param rnr Region number to be cleared.
|
{
|
||||||
*/
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
}
|
||||||
{
|
|
||||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
#ifdef MPU_NS
|
||||||
}
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
#endif
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
/** Configure the given MPU region of the given MPU.
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
* \param mpu Pointer to MPU to be used.
|
{
|
||||||
* \param rnr Region number to be configured.
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
* \param rbar Value for RBAR register.
|
}
|
||||||
* \param rlar Value for RLAR register.
|
#endif
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
/** Configure the given MPU region of the given MPU.
|
||||||
{
|
* \param mpu Pointer to MPU to be used.
|
||||||
mpu->RNR = rnr;
|
* \param rnr Region number to be configured.
|
||||||
mpu->RBAR = rbar;
|
* \param rbar Value for RBAR register.
|
||||||
mpu->RLAR = rlar;
|
* \param rlar Value for RLAR register.
|
||||||
}
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
/** Configure the given MPU region.
|
{
|
||||||
* \param rnr Region number to be configured.
|
mpu->RNR = rnr;
|
||||||
* \param rbar Value for RBAR register.
|
mpu->RBAR = rbar;
|
||||||
* \param rlar Value for RLAR register.
|
mpu->RLAR = rlar;
|
||||||
*/
|
}
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
|
||||||
{
|
/** Configure the given MPU region.
|
||||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
* \param rnr Region number to be configured.
|
||||||
}
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
#ifdef MPU_NS
|
*/
|
||||||
/** Configure the given Non-secure MPU region.
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
* \param rnr Region number to be configured.
|
{
|
||||||
* \param rbar Value for RBAR register.
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
* \param rlar Value for RLAR register.
|
}
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
#ifdef MPU_NS
|
||||||
{
|
/** Configure the given Non-secure MPU region.
|
||||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
* \param rnr Region number to be configured.
|
||||||
}
|
* \param rbar Value for RBAR register.
|
||||||
#endif
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
* \param dst Destination data is copied to.
|
{
|
||||||
* \param src Source data is copied from.
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
* \param len Amount of data words to be copied.
|
}
|
||||||
*/
|
#endif
|
||||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
|
||||||
{
|
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||||
uint32_t i;
|
* \param dst Destination data is copied to.
|
||||||
for (i = 0U; i < len; ++i)
|
* \param src Source data is copied from.
|
||||||
{
|
* \param len Amount of data words to be copied.
|
||||||
dst[i] = src[i];
|
*/
|
||||||
}
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
}
|
{
|
||||||
|
uint32_t i;
|
||||||
/** Load the given number of MPU regions from a table to the given MPU.
|
for (i = 0U; i < len; ++i)
|
||||||
* \param mpu Pointer to the MPU registers to be used.
|
{
|
||||||
* \param rnr First region number to be configured.
|
dst[i] = src[i];
|
||||||
* \param table Pointer to the MPU configuration table.
|
}
|
||||||
* \param cnt Amount of regions to be configured.
|
}
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
{
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
* \param rnr First region number to be configured.
|
||||||
if (cnt == 1U) {
|
* \param table Pointer to the MPU configuration table.
|
||||||
mpu->RNR = rnr;
|
* \param cnt Amount of regions to be configured.
|
||||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
*/
|
||||||
} else {
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
{
|
||||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
mpu->RNR = rnrBase;
|
mpu->RNR = rnr;
|
||||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
} else {
|
||||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
table += c;
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
cnt -= c;
|
|
||||||
rnrOffset = 0U;
|
mpu->RNR = rnrBase;
|
||||||
rnrBase += MPU_TYPE_RALIASES;
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
mpu->RNR = rnrBase;
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
}
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
cnt -= c;
|
||||||
}
|
rnrOffset = 0U;
|
||||||
}
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
/** Load the given number of MPU regions from a table.
|
}
|
||||||
* \param rnr First region number to be configured.
|
|
||||||
* \param table Pointer to the MPU configuration table.
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
* \param cnt Amount of regions to be configured.
|
}
|
||||||
*/
|
}
|
||||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
|
||||||
{
|
/** Load the given number of MPU regions from a table.
|
||||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
* \param rnr First region number to be configured.
|
||||||
}
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
#ifdef MPU_NS
|
*/
|
||||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
* \param rnr First region number to be configured.
|
{
|
||||||
* \param table Pointer to the MPU configuration table.
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
* \param cnt Amount of regions to be configured.
|
}
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
#ifdef MPU_NS
|
||||||
{
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
* \param rnr First region number to be configured.
|
||||||
}
|
* \param table Pointer to the MPU configuration table.
|
||||||
#endif
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
#endif
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|||||||
@@ -0,0 +1,206 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file pac_armv81.h
|
||||||
|
* @brief CMSIS PAC key functions for Armv8.1-M PAC extension
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 23. March 2022
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef PAC_ARMV81_H
|
||||||
|
#define PAC_ARMV81_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### PAC Key functions ########################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
|
||||||
|
\brief Functions that access the PAC keys.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief read the PAC key used for privileged mode
|
||||||
|
\details Reads the PAC key stored in the PAC_KEY_P registers.
|
||||||
|
\param [out] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"mrs r1, pac_key_p_0\n"
|
||||||
|
"str r1,[%0,#0]\n"
|
||||||
|
"mrs r1, pac_key_p_1\n"
|
||||||
|
"str r1,[%0,#4]\n"
|
||||||
|
"mrs r1, pac_key_p_2\n"
|
||||||
|
"str r1,[%0,#8]\n"
|
||||||
|
"mrs r1, pac_key_p_3\n"
|
||||||
|
"str r1,[%0,#12]\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief write the PAC key used for privileged mode
|
||||||
|
\details writes the given PAC key to the PAC_KEY_P registers.
|
||||||
|
\param [in] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"ldr r1,[%0,#0]\n"
|
||||||
|
"msr pac_key_p_0, r1\n"
|
||||||
|
"ldr r1,[%0,#4]\n"
|
||||||
|
"msr pac_key_p_1, r1\n"
|
||||||
|
"ldr r1,[%0,#8]\n"
|
||||||
|
"msr pac_key_p_2, r1\n"
|
||||||
|
"ldr r1,[%0,#12]\n"
|
||||||
|
"msr pac_key_p_3, r1\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief read the PAC key used for unprivileged mode
|
||||||
|
\details Reads the PAC key stored in the PAC_KEY_U registers.
|
||||||
|
\param [out] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"mrs r1, pac_key_u_0\n"
|
||||||
|
"str r1,[%0,#0]\n"
|
||||||
|
"mrs r1, pac_key_u_1\n"
|
||||||
|
"str r1,[%0,#4]\n"
|
||||||
|
"mrs r1, pac_key_u_2\n"
|
||||||
|
"str r1,[%0,#8]\n"
|
||||||
|
"mrs r1, pac_key_u_3\n"
|
||||||
|
"str r1,[%0,#12]\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief write the PAC key used for unprivileged mode
|
||||||
|
\details writes the given PAC key to the PAC_KEY_U registers.
|
||||||
|
\param [in] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"ldr r1,[%0,#0]\n"
|
||||||
|
"msr pac_key_u_0, r1\n"
|
||||||
|
"ldr r1,[%0,#4]\n"
|
||||||
|
"msr pac_key_u_1, r1\n"
|
||||||
|
"ldr r1,[%0,#8]\n"
|
||||||
|
"msr pac_key_u_2, r1\n"
|
||||||
|
"ldr r1,[%0,#12]\n"
|
||||||
|
"msr pac_key_u_3, r1\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief read the PAC key used for privileged mode (non-secure)
|
||||||
|
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
|
||||||
|
\param [out] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"mrs r1, pac_key_p_0_ns\n"
|
||||||
|
"str r1,[%0,#0]\n"
|
||||||
|
"mrs r1, pac_key_p_1_ns\n"
|
||||||
|
"str r1,[%0,#4]\n"
|
||||||
|
"mrs r1, pac_key_p_2_ns\n"
|
||||||
|
"str r1,[%0,#8]\n"
|
||||||
|
"mrs r1, pac_key_p_3_ns\n"
|
||||||
|
"str r1,[%0,#12]\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief write the PAC key used for privileged mode (non-secure)
|
||||||
|
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
|
||||||
|
\param [in] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"ldr r1,[%0,#0]\n"
|
||||||
|
"msr pac_key_p_0_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#4]\n"
|
||||||
|
"msr pac_key_p_1_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#8]\n"
|
||||||
|
"msr pac_key_p_2_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#12]\n"
|
||||||
|
"msr pac_key_p_3_ns, r1\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief read the PAC key used for unprivileged mode (non-secure)
|
||||||
|
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
|
||||||
|
\param [out] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"mrs r1, pac_key_u_0_ns\n"
|
||||||
|
"str r1,[%0,#0]\n"
|
||||||
|
"mrs r1, pac_key_u_1_ns\n"
|
||||||
|
"str r1,[%0,#4]\n"
|
||||||
|
"mrs r1, pac_key_u_2_ns\n"
|
||||||
|
"str r1,[%0,#8]\n"
|
||||||
|
"mrs r1, pac_key_u_3_ns\n"
|
||||||
|
"str r1,[%0,#12]\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief write the PAC key used for unprivileged mode (non-secure)
|
||||||
|
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
|
||||||
|
\param [in] pPacKey 128bit PAC key
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||||
|
__ASM volatile (
|
||||||
|
"ldr r1,[%0,#0]\n"
|
||||||
|
"msr pac_key_u_0_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#4]\n"
|
||||||
|
"msr pac_key_u_1_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#8]\n"
|
||||||
|
"msr pac_key_u_2_ns, r1\n"
|
||||||
|
"ldr r1,[%0,#12]\n"
|
||||||
|
"msr pac_key_u_3_ns, r1\n"
|
||||||
|
: : "r" (pPacKey) : "memory", "r1"
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
|
||||||
|
|
||||||
|
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_PacKeyFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* PAC_ARMV81_H */
|
||||||
@@ -0,0 +1,337 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file pmu_armv8.h
|
||||||
|
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 15. April 2020
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_PMU_ARMV8_H
|
||||||
|
#define ARM_PMU_ARMV8_H
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief PMU Events
|
||||||
|
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||||
|
* */
|
||||||
|
|
||||||
|
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||||
|
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||||
|
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||||
|
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||||
|
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||||
|
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||||
|
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||||
|
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||||
|
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||||
|
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||||
|
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||||
|
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||||
|
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||||
|
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||||
|
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||||
|
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||||
|
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||||
|
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||||
|
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||||
|
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||||
|
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||||
|
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||||
|
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||||
|
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||||
|
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||||
|
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||||
|
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||||
|
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||||
|
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||||
|
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||||
|
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||||
|
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||||
|
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||||
|
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||||
|
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||||
|
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||||
|
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||||
|
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||||
|
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||||
|
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||||
|
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||||
|
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||||
|
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||||
|
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||||
|
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||||
|
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||||
|
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||||
|
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||||
|
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||||
|
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||||
|
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||||
|
|
||||||
|
/** \brief PMU Functions */
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable the PMU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable the PMU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set event to count for PMU eventer counter
|
||||||
|
\param [in] num Event counter (0-30) to configure
|
||||||
|
\param [in] type Event to count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||||
|
{
|
||||||
|
PMU->EVTYPER[num] = type;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reset cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reset all event counters
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable counters
|
||||||
|
\param [in] mask Counters to enable
|
||||||
|
\note Enables one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->CNTENSET = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable counters
|
||||||
|
\param [in] mask Counters to enable
|
||||||
|
\note Disables one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->CNTENCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read cycle counter
|
||||||
|
\return Cycle count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||||
|
{
|
||||||
|
return PMU->CCNTR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read event counter
|
||||||
|
\param [in] num Event counter (0-30) to read
|
||||||
|
\return Event count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||||
|
{
|
||||||
|
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read counter overflow status
|
||||||
|
\return Counter overflow status bits for the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||||
|
{
|
||||||
|
return PMU->OVSSET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear counter overflow status
|
||||||
|
\param [in] mask Counter overflow status bits to clear
|
||||||
|
\note Clears overflow status bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->OVSCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable counter overflow interrupt request
|
||||||
|
\param [in] mask Counter overflow interrupt request bits to set
|
||||||
|
\note Sets overflow interrupt request bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->INTENSET = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable counter overflow interrupt request
|
||||||
|
\param [in] mask Counter overflow interrupt request bits to clear
|
||||||
|
\note Clears overflow interrupt request bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->INTENCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Software increment event counter
|
||||||
|
\param [in] mask Counters to increment
|
||||||
|
\note Software increment bits for one or more event counters (0-30)
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->SWINC = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -1,70 +1,70 @@
|
|||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
* @file tz_context.h
|
* @file tz_context.h
|
||||||
* @brief Context Management for Armv8-M TrustZone
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
* @version V1.0.1
|
* @version V1.0.1
|
||||||
* @date 10. January 2018
|
* @date 10. January 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*
|
*
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
* not use this file except in compliance with the License.
|
* not use this file except in compliance with the License.
|
||||||
* You may obtain a copy of the License at
|
* You may obtain a copy of the License at
|
||||||
*
|
*
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
*
|
*
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
* See the License for the specific language governing permissions and
|
* See the License for the specific language governing permissions and
|
||||||
* limitations under the License.
|
* limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined (__clang__)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef TZ_CONTEXT_H
|
#ifndef TZ_CONTEXT_H
|
||||||
#define TZ_CONTEXT_H
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#ifndef TZ_MODULEID_T
|
#ifndef TZ_MODULEID_T
|
||||||
#define TZ_MODULEID_T
|
#define TZ_MODULEID_T
|
||||||
/// \details Data type that identifies secure software modules called by a process.
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
typedef uint32_t TZ_ModuleId_t;
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
typedef uint32_t TZ_MemoryId_t;
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
/// Initialize secure context memory system
|
/// Initialize secure context memory system
|
||||||
/// \return execution status (1: success, 0: error)
|
/// \return execution status (1: success, 0: error)
|
||||||
uint32_t TZ_InitContextSystem_S (void);
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
/// Allocate context memory for calling secure software modules in TrustZone
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
/// \param[in] module identifies software modules called from non-secure mode
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
/// \return value != 0 id TrustZone memory slot identifier
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
/// \return value 0 no memory available or internal error
|
/// \return value 0 no memory available or internal error
|
||||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
/// \param[in] id TrustZone memory slot identifier
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
/// \return execution status (1: success, 0: error)
|
/// \return execution status (1: success, 0: error)
|
||||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
/// Load secure context (called on RTOS thread context switch)
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
/// \param[in] id TrustZone memory slot identifier
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
/// \return execution status (1: success, 0: error)
|
/// \return execution status (1: success, 0: error)
|
||||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
/// Store secure context (called on RTOS thread context switch)
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
/// \param[in] id TrustZone memory slot identifier
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
/// \return execution status (1: success, 0: error)
|
/// \return execution status (1: success, 0: error)
|
||||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
#endif // TZ_CONTEXT_H
|
#endif // TZ_CONTEXT_H
|
||||||
|
|||||||
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