CHG programming further investigation
This commit is contained in:
Tom Kuschel
@ -105,12 +105,15 @@ typedef enum {
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#ifndef SI5351_NUMBER_OF_OUTPUTS
|
||||
#define SI5351_NUMBER_OF_OUTPUTS 8
|
||||
#endif
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
si5351_inst_t si5351_init(void * i2c_handle, uint32_t xtal_frequency, uint8_t i2c_address);
|
||||
int si5351_deinit(si5351_inst_t si5351_handle);
|
||||
int si5351_isready(si5351_inst_t inst);
|
||||
int si5351_program(si5351_inst_t inst);
|
||||
char * si5351_read_debug_msg(si5351_inst_t inst);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern "C" */
|
||||
|
||||
@ -68,9 +68,17 @@
|
||||
#define SI5351_CLK0_SRC_1 (1u<<3) /* Output Clock 0 Input Source */
|
||||
#define SI5351_CLK0_SRC_0 (1u<<2) /* 00: Select the XTAL as the clock source for CLK0. By-pass both synthesis stages (PLL/VCXO & MultiSynth) */
|
||||
#define SI5351_CLK0_SRC (3u<<2) /* and connects CLK0 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK_SRC_XTAL (0x00<<2) /*!< Select the XTAL as the clock source for CLKx */
|
||||
#define SI5351_CLK_SRC_CLKIN (0x01<<2) /*!< Select the CLKIN as the clock source for CLKx */
|
||||
#define SI5351_CLK_SRC_MS0 (0x02<<2) /*!< Select the MulitSynth 0 as the clock source for CLKx */
|
||||
#define SI5351_CLK_SRC_MS1 (0x03<<2) /*!< Select the MulitSynth 1 as the clock source for CLKx */
|
||||
#define SI5351_CLK0_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK0. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 0 as source for CLK0 */
|
||||
#define SI5351_CLK0_IDRV_0 (1u<<0) /* CLK0 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK0_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK0_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK_2_MA (0x00) /*!< 2 mA output rise and fall time / drive strength control */
|
||||
#define SI5351_CLK_4_MA (0x01) /*!< 4 mA output rise and fall time / drive strength control */
|
||||
#define SI5351_CLK_6_MA (0x02) /*!< 6 mA output rise and fall time / drive strength control */
|
||||
#define SI5351_CLK_8_MA (0x03) /*!< 8 mA output rise and fall time / drive strength control */
|
||||
#define SI5351_CLK0_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK1_CONTROL 17u /* R/W */
|
||||
@ -83,7 +91,7 @@
|
||||
#define SI5351_CLK1_SRC (3u<<2) /* and connects CLK1 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK1_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK1. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 1 as source for CLK1 */
|
||||
#define SI5351_CLK1_IDRV_0 (1u<<0) /* CLK1 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK1_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK1_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK1_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK2_CONTROL 18u /* R/W */
|
||||
@ -96,7 +104,7 @@
|
||||
#define SI5351_CLK2_SRC (3u<<2) /* and connects CLK2 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK2_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK2. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 2 as source for CLK2 */
|
||||
#define SI5351_CLK2_IDRV_0 (1u<<0) /* CLK2 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK2_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK2_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK2_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK3_CONTROL 19u /* R/W */
|
||||
@ -109,7 +117,7 @@
|
||||
#define SI5351_CLK3_SRC (3u<<2) /* and connects CLK3 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK3_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK3. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 3 as source for CLK3 */
|
||||
#define SI5351_CLK3_IDRV_0 (1u<<0) /* CLK3 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK3_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK3_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK3_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK4_CONTROL 20u /* R/W */
|
||||
@ -122,7 +130,7 @@
|
||||
#define SI5351_CLK4_SRC (3u<<2) /* and connects CLK4 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK4_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK4. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 4 as source for CLK4 */
|
||||
#define SI5351_CLK4_IDRV_0 (1u<<0) /* CLK4 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK4_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK4_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK4_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK5_CONTROL 21u /* R/W */
|
||||
@ -135,12 +143,13 @@
|
||||
#define SI5351_CLK5_SRC (3u<<2) /* and connects CLK5 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK5_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK5. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 5 as source for CLK5 */
|
||||
#define SI5351_CLK5_IDRV_0 (1u<<0) /* CLK5 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK5_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK5_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK5_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK6_CONTROL 22u /* R/W */
|
||||
#define SI5351_CLK6_PDN (1u<<7) /* Clock 6 Power Down. */
|
||||
#define SI5351_MS6_INT (1u<<6) /* MultiSynth 6 Integer Mode. 1..MS6 operates in integer mode. */
|
||||
/* #define SI5351_MS6_INT (1u<<6) */
|
||||
#define SI5351_FBA_INT (1u<<6) /*!< FBA MultiSynth Integer Mode. 1..MSNA operates in integer mode */
|
||||
#define SI5351_MS6_SRC (1u<<5) /* MultiSynth Source Select for CLK6 */
|
||||
#define SI5351_CLK6_INV (1u<<4) /* Output Clock 6 Invert. */
|
||||
#define SI5351_CLK6_SRC_1 (1u<<3) /* Output Clock 6 Input Source */
|
||||
@ -148,12 +157,13 @@
|
||||
#define SI5351_CLK6_SRC (3u<<2) /* and connects CLK6 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK6_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK6. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 6 as source for CLK6 */
|
||||
#define SI5351_CLK6_IDRV_0 (1u<<0) /* CLK6 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK6_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK6_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK6_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK7_CONTROL 23u /* R/W */
|
||||
#define SI5351_CLK7_PDN (1u<<7) /* Clock 7 Power Down. */
|
||||
#define SI5351_MS7_INT (1u<<6) /* MultiSynth 7 Integer Mode. 1..MS7 operates in integer mode. */
|
||||
/* #define SI5351_MS7_INT (1u<<6) */
|
||||
#define SI5351_FBB_INT (1u<<6) /*!< FBB Multisynth Integer Mode. 1..MSNB operates in integer mode */
|
||||
#define SI5351_MS7_SRC (1u<<5) /* MultiSynth Source Select for CLK7 */
|
||||
#define SI5351_CLK7_INV (1u<<4) /* Output Clock 7 Invert. */
|
||||
#define SI5351_CLK7_SRC_1 (1u<<3) /* Output Clock 7 Input Source */
|
||||
@ -161,7 +171,7 @@
|
||||
#define SI5351_CLK7_SRC (3u<<2) /* and connects CLK7 directly to the oscillator which generates an output freq determined by the XTAL freq. */
|
||||
#define SI5351_CLK7_IDRV_1 (1u<<1) /* 01: CLKIN as clock source for CLK7. By-pass both synthesis stages. 10: N/A. 11: Select MultiSynth 7 as source for CLK7 */
|
||||
#define SI5351_CLK7_IDRV_0 (1u<<0) /* CLK7 Output Rise and Fall time / Drive Strength Control */
|
||||
#define SI5551_CLK7_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK7_IDRV (3u<<0) /* 00: 2 mA, 01: 4 mA, 10: 6 mA, 11: 8 mA */
|
||||
#define SI5351_CLK7_CONTROL_RESET_VALUE 0x00
|
||||
|
||||
#define SI5351_CLK3_0_DISABLE_STATE 24u /* R/W */
|
||||
@ -1079,3 +1089,21 @@ even integers greater than or equal to 6. All other divide values are invalid. *
|
||||
#define R6_DIV (7u<<4)
|
||||
|
||||
|
||||
/* Crystal Internal Load Capacitance
|
||||
* Two bits determine the internal load capacitance value for the crystal. See the Crystal
|
||||
* Inputs section in the Si5351 data sheet
|
||||
* Default: SI5351_XTAL_CL_10_PF (10 pF load capacitors)
|
||||
*/
|
||||
#define SI5351_CRYSTAL_INTERNAL_LOAD_CAPACITANCE 183u /* R/W */
|
||||
#define SI5351_XTAL_CL_6_PF (1u<<6) /*!< Internal CL = 6 pF */
|
||||
#define SI5351_XTAL_CL_8_PF (2u<<6) /*!< Internal CL = 8 pF */
|
||||
#define SI5351_XTAL_CL_10_PF (3u<<6) /*!< Internal CL = 10 pF */
|
||||
#define SI5351_XTAL_CL_MASK (3u<<6) /*!< Mask of the load capacitance */
|
||||
#define SI5351_XTAL_RESERVED (0x13) /*!< RESERVED bit[5:0] should be written! */
|
||||
/* Fanout Enable, set these bits to 1 for each fanout
|
||||
* note: the reset value of this SI5351 register is 0x00 */
|
||||
|
||||
#define SI5351_FANOUT_ENABLE 187u /* R/W */
|
||||
#define SI5351_CLKIN_FANOUT_EN (1u<<7) /*!< Enable fanout of CLKIN to clock output multiplexers. Set it to 1 */
|
||||
#define SI5351_XO_FANOUT_EN (1u<<6) /*!< Enable fanout of XO to clock output multiplexers. Set it to 1 */
|
||||
#define SI5351_MS_FANOUT_EN (1u<<4) /*!< Enable fanout of Multisynth0 & Multisynth4 to all output multiplexers. Set it to 1 */
|
||||
|
||||
Reference in New Issue
Block a user